3D-vias aware quadratic placement for 3D VLSI circuits

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 67-72

  Hentschke, Renato ^a   Flach, Guilherme ^a   Pinto, Felipe ^a   Reis, Ricardo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATION;

3D-VIAS COUNT; FASTPLACE ALGORITHM; ITERATIVE REFINEMENT; QUADRATIC PLACEMENT;

VLSI CIRCUITS;

EID: 36348937183     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.1     Document Type: Conference Paper

References (14)

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