An algorithm for I/O partitioning targeting 3D circuits and its impact on 3D-vias

IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip

Volumn , Issue , 2006, Pages 128-133

  Hentschke, Renato ^a   Sawicki, Sandro ^a   Johann, Marcelo ^a   Reis, Ricardo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BOOLEAN FUNCTIONS; FOOD PRESERVATION; INTEGRATED CIRCUITS; LSI CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS;

(PL) PROPERTIES; BALANCE (WEIGHTING); EXPERIMENTAL RESULTS; I/O PINS; INTERNATIONAL CONFERENCES; MIN-CUT; NET LIST; PARTITIONING ALGORITHMS; SYSTEM ON CHIP (SOCS); THREE-DIMENSIONAL (3D) CIRCUITS; VERY LARGE SCALE INTEGRATION (VLSI);

ALGORITHMS;

EID: 46249104007     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2006.313216     Document Type: Conference Paper

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