Electro-physical technique for post-fabrication measurements of CMOS process layer thicknesses

Journal of Research of the National Institute of Standards and Technology

Volumn 112, Issue 5, 2007, Pages 223-256

  Marshall, Janet C ^a   Vernier, P Thomas ^b  

^a NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

CMOS; MEMS; Nomenclature; Platform height; Step height; Test structures; Thickness; Young's modulus

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELASTIC MODULI; MEASUREMENT THEORY; SHEET RESISTANCE; TERMINOLOGY; UNCERTAINTY ANALYSIS;

DIELECTRIC THICKNESS; PLATFORM HEIGHT; STEP HEIGHT; TEST STRUCTURES;

THICKNESS CONTROL;

EID: 36249001307     PISSN: 1044677X     EISSN: None     Source Type: Journal    
DOI: 10.6028/jres.112.018     Document Type: Article

References (18)

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