-
2
-
-
0036803456
-
-
0.3As HEMTs with an ultrahigh ft of 562 GHz, IEEE Electron Device Lett., 23, no. 10, pp. 573-575, Oct. 2002.
-
0.3As HEMTs with an ultrahigh ft of 562 GHz," IEEE Electron Device Lett., vol. 23, no. 10, pp. 573-575, Oct. 2002.
-
-
-
-
3
-
-
2442482780
-
0.48As HEMTs with reduced source and drain resistance
-
May
-
0.48As HEMTs with reduced source and drain resistance," IEEE Electron Device Lett., vol. 25, no. 5, pp. 241-243, May 2004.
-
(2004)
IEEE Electron Device Lett
, vol.25
, Issue.5
, pp. 241-243
-
-
Shinohara, K.1
Yamashita, Y.2
Endoh, A.3
Watanable, I.4
Hikosaka, K.5
Matsui, T.6
Mimura, T.7
Hiyamizu, S.8
-
4
-
-
2942741319
-
InAlAs-InGaAs double-gate HEMTs on transferred substrate
-
Jun
-
N. Wichmann, I. Duszynski, X. Wallart, S. Bollaert, and A. Cappy, "InAlAs-InGaAs double-gate HEMTs on transferred substrate," IEEE Electron Device Lett., vol. 25, no. 6, pp. 354-356, Jun. 2004.
-
(2004)
IEEE Electron Device Lett
, vol.25
, Issue.6
, pp. 354-356
-
-
Wichmann, N.1
Duszynski, I.2
Wallart, X.3
Bollaert, S.4
Cappy, A.5
-
5
-
-
21644457972
-
100 nm InAlAs/InGaAs double-gate HEMT using transferred substrate
-
Dec
-
N. Wichmann, I. Duszynski, S. Bollaert, J. Mateos, X. Wallart, and A. Cappy, "100 nm InAlAs/InGaAs double-gate HEMT using transferred substrate," in IEDM Tech. Dig., Dec. 2004, pp. 1023-1026.
-
(2004)
IEDM Tech. Dig
, pp. 1023-1026
-
-
Wichmann, N.1
Duszynski, I.2
Bollaert, S.3
Mateos, J.4
Wallart, X.5
Cappy, A.6
-
6
-
-
26444529869
-
0.48As double-gate HEMTs with two separate gate controls
-
Sep
-
0.48As double-gate HEMTs with two separate gate controls," IEEE Electron Device Lett., vol. 26, no. 9, pp. 601-603, Sep. 2005.
-
(2005)
IEEE Electron Device Lett
, vol.26
, Issue.9
, pp. 601-603
-
-
Wichmann, N.1
Duszynski, I.2
Wallart, X.3
Bollaert, S.4
Cappy, A.5
-
7
-
-
0023421993
-
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
-
Sep
-
F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 410-412, Sep. 1987.
-
(1987)
IEEE Electron Device Lett
, vol.EDL-8
, Issue.9
, pp. 410-412
-
-
Balestra, F.1
Cristoloveanu, S.2
Benachir, M.3
Brini, J.4
Elewa, T.5
-
8
-
-
85056911965
-
Monte Carlo simulation of a 30 nm dual-gate MOSFET: How far can Si go?
-
D. Frank, S. Laux, and M. Fishetti, "Monte Carlo simulation of a 30 nm dual-gate MOSFET: How far can Si go?" in IEDM Tech. Dig., 1992, pp. 553-598
-
(1992)
IEDM Tech. Dig
, pp. 553-598
-
-
Frank, D.1
Laux, S.2
Fishetti, M.3
-
9
-
-
0028756972
-
Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs
-
H. S. Wong, D. J. Frank, Y. Taur, and J. M. C. Stork, "Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs," in IEDM Tech. Dig., 1994, pp. 747-751.
-
(1994)
IEDM Tech. Dig
, pp. 747-751
-
-
Wong, H.S.1
Frank, D.J.2
Taur, Y.3
Stork, J.M.C.4
-
10
-
-
0033909161
-
Improved Monte Carlo algorithm for the simulation of δ-doped AllnAs/GaInAs HEMTs
-
Jan
-
J. Mateos, T. González, D. Pardo, V. Hoël, H. Happy, and A. Cappy, "Improved Monte Carlo algorithm for the simulation of δ-doped AllnAs/GaInAs HEMTs," IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 250-253, Jan. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.1
, pp. 250-253
-
-
Mateos, J.1
González, T.2
Pardo, D.3
Hoël, V.4
Happy, H.5
Cappy, A.6
-
11
-
-
0034297790
-
Monte Carlo simulator for the design optimization of low-noise HEMTs
-
Oct
-
J. Mateos, T. González, D. Pardo, V. Hoël, and A. Cappy, "Monte Carlo simulator for the design optimization of low-noise HEMTs," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1950-1956, Oct. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.10
, pp. 1950-1956
-
-
Mateos, J.1
González, T.2
Pardo, D.3
Hoël, V.4
Cappy, A.5
-
12
-
-
11144355224
-
Design optimization of AllnAs-GaInAs HEMTs for high-frequency applications
-
Apr
-
J. Mateos, T. González, D. Pardo, S. Bollaert, T. Parenty, and A. Cappy, "Design optimization of AllnAs-GaInAs HEMTs for high-frequency applications," IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 521-528, Apr. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.4
, pp. 521-528
-
-
Mateos, J.1
González, T.2
Pardo, D.3
Bollaert, S.4
Parenty, T.5
Cappy, A.6
-
13
-
-
0029292268
-
Monte Carlo determination of the intrinsic small-signal equivalent circuit of MESFETs
-
Apr
-
T. González and D. Pardo, "Monte Carlo determination of the intrinsic small-signal equivalent circuit of MESFETs," IEEE Trans. Electron Devices, vol. 42, no. 4, pp. 605-611, Apr. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, Issue.4
, pp. 605-611
-
-
González, T.1
Pardo, D.2
|