Architectural design of a fast floating-point multiplication-add fused unit using signed-digit addition

Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001

Volumn , Issue , 2001, Pages 346-353

  Chen, Chichyang ^a   Chen, Liang An ^a   Cheng, Jih Ren ^a  

^a FENG CHIA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; DIGITAL ARITHMETIC; RECONFIGURABLE HARDWARE; SYSTEMS ANALYSIS;

CARRY PROPAGATION; FLOATING POINT MULTIPLICATION; FLOATING POINTS; NORMALIZATION METHODS; SIGN DETECTION; SIGNED DIGITS; SINGLE WORDS; VERILOG HARDWARE DESCRIPTION LANGUAGES;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 84969498435     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2001.952324     Document Type: Conference Paper

References (8)

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7. T. Stouraitis and C. Chen, "Fast Digit-Parallel Conversion of Signed Digit into Conventional Representations," Electronics Letters, vol. 27, no. 11, pp. 964-965, May 1991.
8. Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakese, Koichiro Mashiko, and Tadashi Sumi, "Leading-Zero Anticipatory Logic for High-Speed Floating-Point Addition," IEEE Journal of Solid State Circuits, vol. 31, no. 8, pp. 1157-1164, Aug. 1996.