A flexible arithmetic and logic unit for multimedia processing

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5205, Issue , 2003, Pages 520-528

  Senthilvelan, Murugappan ^a   Schulte, Michael J ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Adder; ALU; Computer arithmetic; DSP; Multimedia; Saturating

Indexed keywords

ADDERS; COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; DIGITAL SIGNAL PROCESSING; IMAGE COMPRESSION; LOGIC DEVICES; MULTIMEDIA SYSTEMS; PARALLEL PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING;

ARITHMETIC AND LOGIC UNIT; COMPUTER ARITHMETIC; DIGITAL SIGNAL PROCESSORS; SINGLE INSTRUCTION MULTIPLE DATA PROCESSING;

DIGITAL ARITHMETIC;

EID: 1842525757     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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