A design for testability scheme for CMOS LC-tank voltage controlled oscillators

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 20, Issue 2, 2004, Pages 133-142

  Dermentzoglou, Lampros ^a   Tsiatouhas, Yiorgos ^b   Arapoyanni, Angela ^a  

^a UNIVERSITY OF ATHENS   (Greece)

^b UNIVERSITY OF IOANNINA   (Greece)

Author keywords

Design for Testability (DFT); Radio Frequency (RF) Testing; Voltage Controlled Oscillator (VCOs)

Indexed keywords

ACOUSTIC NOISE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; MONTE CARLO METHODS; PHASE LOCKED LOOPS; Q FACTOR MEASUREMENT; STATISTICAL METHODS; TRANSCEIVERS; VARACTORS; WIRELESS TELECOMMUNICATION SYSTEMS;

CIRCUIT RESPONSE; CIRCUIT UNDER TEST (CUT); PHASE NOISE; RADIO FREQUENCY (RF) TESTING;

VARIABLE FREQUENCY OSCILLATORS;

EID: 3543080937     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:JETT.0000023677.58861.81     Document Type: Article

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