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IEEE Design and Test of Computers

Volumn 24, Issue 5, 2007, Pages 442-452

Adaptive latency-insensitive protocols

(2) Casu, Mario R a Macchiarulo, Luca b

a POLITECNICO DI TORINO (Italy)

b University of Hawaii at Manoa (United States)

Author keywords

Delay; ICs; Interconnections; Latency insensitive protocols; Pipeline processing; Protocols; Radiation detectors; Synchronization; Wire pipelining

Indexed keywords

INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MOTION PICTURE EXPERTS GROUP STANDARDS; RADIATION DETECTORS; SYNCHRONIZATION;

LATENCY-INSENSITIVE PROTOCOLS; SYNCHRONOUS LOGIC BLOCKS;

PIPELINE PROCESSING SYSTEMS;

EID: 35348882069 PISSN: 07407475 EISSN: None Source Type: Journal
DOI: 10.1109/MDT.2007.152 Document Type: Article

Times cited : (21)

References (7)

1
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- M.R. Casu and L. Macchiarulo, "A New Approach to Latency Insensitive Design," Proc. 41st Design Automation Conf. (DAC 04), ACM Press, 2004, pp. 576-581.
- (2004) Proc. 41st Design Automation Conf. (DAC 04) , pp. 576-581
- Casu, M.R.¹ Macchiarulo, L.²

2
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- Throughput-Driven Floorplanning with Wire Pipelining
- May
- M.R. Casu and L. Macchiarulo, "Throughput-Driven Floorplanning with Wire Pipelining," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 5, May 2005, pp. 663-675.
- (2005) IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems , vol.24 , Issue.5 , pp. 663-675
- Casu, M.R.¹ Macchiarulo, L.²

3
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- Floorplanning with Wire Pipelining in Adaptive Communication Channels
- Dec
- M.R. Casu and L. Macchiarulo, "Floorplanning with Wire Pipelining in Adaptive Communication Channels," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, Dec. 2006, pp. 2996-3004.
- (2006) IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems , vol.25 , Issue.12 , pp. 2996-3004
- Casu, M.R.¹ Macchiarulo, L.²

4
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- Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
- IEEE CS Press
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- (2004) Proc. Design, Automation and Test in Europe Conf. (DATE 04) , vol.2 , pp. 1008-1013
- Singh, M.¹ Theobald, M.²

5
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- Performance Analysis and Optimization of Latency Insensitive Systems
- ACM Press
- L.P. Carloni and A. Sangiovanni-Vincentelli, "Performance Analysis and Optimization of Latency Insensitive Systems," Proc. 37th Design Automation Conf. (DAC 00), ACM Press, 2000, pp. 361-367.
- (2000) Proc. 37th Design Automation Conf. (DAC 00) , pp. 361-367
- Carloni, L.P.¹ Sangiovanni-Vincentelli, A.²

6
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- An Architecture and a Wrapper Synthesis Approach for Multi-Clock Latency-Insensitive Systems
- IEEE CS Press, pp
- A. Agiwal and M. Singh, "An Architecture and a Wrapper Synthesis Approach for Multi-Clock Latency-Insensitive Systems," Proc. Int'l Conf. Computer-Aided Design (ICCAD 05), IEEE CS Press, pp. 1006-1013.
- Proc. Int'l Conf. Computer-Aided Design (ICCAD 05) , pp. 1006-1013
- Agiwal, A.¹ Singh, M.²

7
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- SuperENC: MPEG-2 Video Encoder Chip
- Jul./Aug
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- (1999) IEEE Micro , vol.19 , Issue.4 , pp. 56-65
- Ikeda, M.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.