An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 1006-1013

  Agiwal, Ankur ^a   Singh, Montek ^a  

^a UNIVERSITY OF NORTH CAROLINA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; DATA TRANSFER; INTERFACES (COMPUTER); OPTIMIZATION;

METASTABILITY RESOLUTION; MULTICLOCK LATENCY INSENSITIVE SYSTEMS; MULTICLOCK SYSTEMS ON CHIPS; WRAPPER SYNTHESIS;

CHIP SCALE PACKAGES;

EID: 33751400835     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560209     Document Type: Conference Paper

References (16)

1. M. Singh and M. Theobald, "Generalized latency-insensitive systems for single-clock and multi-clock architectures," in Proc. Design, Automation and Test in Europe (DATE), Feb. 2004.
2. Fujitsu Ltd., Fujitsu Laboratories Ltd., and Hitachi Ltd., "Component wrapper language," http://www.labs.fujitsu.com/en/techinfo/ cwl/index.htm.
3. D. M. Chapiro, "Globally-asynchronous locally-synchronous systems," Ph.D. dissertation, Stanford University, Oct. 1984.
4. L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli, "Latency insensitive protocols," in Computer Aided Verification, 1999, pp. 123-133.
5. L. Carloni, K. McMillan, and A. Sangiovanni-Vincentelli, "The theory of latency insensitive design," IEEE Transactions on Computer-Aided Design, vol. 20, no. 9, September 2001.
6. J. Muttersbach, T. Villiger, and W. Fichtner, "Practical design of globally-asynchronous locally-synchronous systems," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, Apr. 2000, pp. 52-59.
7. K. Y. Yun and R. P. Donohue, "Pausible clocking: A first step toward heterogeneous systems," in Proc. International Conf. Computer Design (ICCD), Oct. 1996.
8. A. Chakraborty and M. R. Greenstreet, "Efficient self-timed interfaces for crossing clock domains," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, May 2003, pp. 78-88.
9. A. Davis and S. M. Nowick, "An introduction to asynchronous circuit design," Dept. of Computer Science, University of Utah, Tech. Rep. UUCS-97-013, Sept. 1997.
10. R. Ginosar, "Fourteen ways to fool your synchronizer," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, May 2003, pp. 89-96.
11. M. Singh and S. M. Nowick, "MOUSETRAP: Ultra-high-speed transition-signaling asynchronous pipelines," in Proc. International Conf. Computer Design (ICCD), Nov. 2001, pp. 9-17.
12. _, "High-throughput asynchronous pipelines for fine-grain dynamic datapaths," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, Apr. 2000, pp. 198-209.
13. I. Sutherland and S. Fairbanks, "GasP: A minimal FIFO control," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, Mar. 2001, pp. 46-53.
14. T. Chelcea and S. M. Nowick, "Robust interfaces for mixed-timing systems with application to latency-insensitive protocols," in Proc. ACM/IEEE Design Automation Conference, June 2001.
15. J. Mekie, S. Chakraborty, and D. K. Sharma, "Evaluation of pausible clocking scheme for interfacing high speed IP cores in GALS framework," in Proc. International Conference on VLSI Design, Jan. 2004.
16. Ellen M. Sentovich, et al., "SIS: a system for sequential circuits synthesis," U.C. Berkeley, Department of EECS Technical Report No. UCB/ERL M92/41, May 1992.