Noise margin in low power SRAM cells

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3254, Issue , 2004, Pages 889-898

  Cserveny, S ^a   Masgonty, J M ^a   Piguet, C ^a  

^a CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

ASYMMETRICAL CELLS; BIT LINES; BODY BIASING; LOW SUPPLY VOLTAGES; LOW-POWER SRAM; NOISE MARGINS; REDUCED POWER CONSUMPTION; SRAM CELL;

STATIC RANDOM ACCESS STORAGE;

EID: 35048862469     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30205-6_91     Document Type: Article

References (12)

1. T. Sakurai, "Perspectives on Power-Aware Electronics", Plenary Talk 1.2, Proc. 1SSCC 2003, San- Francisco, CA, Feb. 9-13,2003, pp. 26-29
2. C. Piguet, S. Cserveny, J.-F. Perotto, J.-M. Masgonty: Techniques de circuits et methodes de conception pour réduire la consommation statique dans les technologies profondément submicroniques, Proc. FTFC'03, pp. 21-29
3. H. Hanson, M.S. Hrishikesh, V. Agarwal, S.W. Keckler, D. Burger, "Static Energy Reduction Techniques for Microprocessor Caches", IEEE Trans. VLSI Systems, vol. 11, pp. 303-313, June 2003
4. A. Agarwal, H. Li, K. Roy, "A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron", IEEE J. Solid-State Circuits, vol. 38, pp. 319-328, Feb. 2003
5. A. Chandrakasan, R. Min, M. Bhardwaj, S. -H. Cho, A. Wang, "Power Aware Wireless Microsensor Systems", Proc. ESSCIRC 2002, pp. 47-54
6. J.-M. Masgonty, S. Cserveny, C. Piguet "Low Power SRAM and ROM Memories", Proc. PATMOS2001, paper 7.4
7. S. Cserveny, J.-M. Masgonty, C. Piguet, F. Robin, "Random Access Memory", US Patent US 6'366'504 Bl, April 2,2002
8. S. Cserveny, J.-M. Masgonty, C. Piguet, "Stand-by Power Reduction for Storage Circuits", in J. J. Cliico and E. Macii (Eds.): PATMOS 2003, LNCS 2799, pp. 229-238, Springer 2003
9. K. Roy, S.Mukhopadhyay, H. Mahmoodi-Meimand, "Leakage Current Mechanism and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuit", Proc. IEEE, vol. 91, pp. 305-327, Feb. 2003
10. A. Agarwal, K. Roy: "A Noise Tolerant Cache Design to Reduce Gate and Sub-threshold Leakage in the Nanometer Regime", Proc. ISLPED'03, pp. 18-21
11. E. Seevinck, F.J. List, J. Lohstroh "Static-Noise Margin Analysis of MOS SRAM Cells", IEEEJ. Solid-State Circuits, vol. 22, pp. 748-754, Oct. 1987
12. A. J. Bhavnagarwala, X. Tang, J. D. Meindl "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability", IEEE J. Solid-State Circuits, vol. 36, pp. 658-665, April 2001