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Volumn 3235, Issue , 2004, Pages 259-275

Witness and counterexample automata for ACTL

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY;

EID: 35048856013     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30232-2_17     Document Type: Article
Times cited : (8)

References (15)
  • 3
    • 0022706656 scopus 로고
    • Automatic Verification of Finite State Concurrent Systems using Temporal Logic Specifications
    • E. M. Clarke, E. A. Emerson, A. P. Sistla. Automatic Verification of Finite State Concurrent Systems using Temporal Logic Specifications. ACM Transaction on Programming Languages and Systems, 8(2), (1986, pp. 244-263.
    • (1986) ACM Transaction on Programming Languages and Systems , vol.8 , Issue.2 , pp. 244-263
    • Clarke, E.M.1    Emerson, E.A.2    Sistla, A.P.3
  • 6
    • 35048817755 scopus 로고    scopus 로고
    • Exploiting Symbolic Model Checking for Sensing Stuck-at Faults in Digital Circuits
    • A. Casar, Z. Brezocnik, T. Kapus. Exploiting Symbolic Model Checking for Sensing Stuck-at Faults in Digital Circuits. Informacije MIDEM, 32(3), 2002, pp. 171-180.
    • (2002) Informacije MIDEM , vol.32 , Issue.3 , pp. 171-180
    • Casar, A.1    Brezocnik, Z.2    Kapus, T.3
  • 7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.