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Volumn 32, Issue 3, 2002, Pages 171-180

Exploiting symbolic model checking for sensing stuck-at faults in digital circuits

Author keywords

Automatic test pattern generation; Binary decision diagrams; CTL formulas; Finite state machine; Stuck at faults; Symbolic model checking; Testing

Indexed keywords


EID: 35048817755     PISSN: 03529045     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (10)
  • 2
    • 0022769976 scopus 로고
    • Graph-based algorithms for boolean function manipulation
    • August
    • Randal E. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, C-35(8):677-691, August 1986.
    • (1986) IEEE Transactions on Computers , vol.C-35 , Issue.8 , pp. 677-691
    • Bryant, R.E.1
  • 4
    • 0342590081 scopus 로고    scopus 로고
    • Symbolic forward/backward traversals of large finite state machines
    • Gianpiero Cabodi, Paolo Camurati, and Stefano Quer. Symbolic forward/backward traversals of large finite state machines. Journal of Systems Architecture, 46:1137-1158, 2000.
    • (2000) Journal of Systems Architecture , vol.46 , pp. 1137-1158
    • Cabodi, G.1    Camurati, P.2    Quer, S.3
  • 5
    • 25744474932 scopus 로고    scopus 로고
    • Master's thesis, University of Maribor, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia, June In Slovene
    • Aleš Časar. Verification of finite state machines with symbolic model checking. Master's thesis, University of Maribor, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia, June 1998. In Slovene.
    • (1998) Verification of Finite State Machines with Symbolic Model Checking
    • Časar, A.1
  • 6
    • 0347934736 scopus 로고    scopus 로고
    • Formal verification of digital circuits using symbolic model checking
    • September
    • Aleš Časar, Zmago Brezočnik, and Tatjana Kapus. Formal Verification of Digital Circuits using Symbolic Model Checking. Informacije MIDEM, 30(3(95)): 153-160, September 2000.
    • (2000) Informacije MIDEM , vol.30 , Issue.3-95 , pp. 153-160
    • Časar, A.1    Brezočnik, Z.2    Kapus, T.3
  • 7
    • 0026997454 scopus 로고
    • Representation of Boolean Functions with ROBDDs
    • December In Slovene
    • Aleš Časar, Robert Meolic, Zmago Brezočnik, and Bogomir Horvat. Representation of Boolean Functions with ROBDDs. Electrotechnical Review, 59(5):299-307, December 1992. In Slovene.
    • (1992) Electrotechnical Review , vol.59 , Issue.5 , pp. 299-307
    • Časar, A.1    Meolic, R.2    Brezočnik, Z.3    Horvat, B.4
  • 9
    • 0022706656 scopus 로고
    • Automatic verification of finite-state concurrent systems using temporal logic specifications
    • April
    • E. M. Clarke, E. A. Emerson, and A. P. Sistla. Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications. ACM Transactions on Programming Languages and Systems, 8(2): 244-263, April 1986.
    • (1986) ACM Transactions on Programming Languages and Systems , vol.8 , Issue.2 , pp. 244-263
    • Clarke, E.M.1    Emerson, E.A.2    Sistla, A.P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.