An auto-adaptative reconfigurable architecture for the control

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3189, Issue , 2004, Pages 72-87

  Ventroux, Nicolas ^a   Chevobbe, Stéphane ^a   Blanc, Fréderic ^a   Collette, Thierry ^a  

^a CEA LIST   (France)

Author keywords

Adaptative reconfigurable architecture; Control parallelism; Dynamic reconfiguration

Indexed keywords

COMPUTER ARCHITECTURE; DYNAMIC MODELS;

DESIGNING COMPLEX; DYNAMIC RE-CONFIGURATION; PROCESSING APPLICATIONS; RECONFIGURABLE DEVICES; RUNTIMES; TECHNOLOGY IMPROVEMENT;

RECONFIGURABLE ARCHITECTURES;

EID: 35048856011     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30102-8_7     Document Type: Article

References (27)

1. Semiconductor Industry Association. International Technology Roadmap for Semiconductors. Technical report, 2003.
2. K. Compton and S. Hauck. Reconfigurable Computing: A Survey of Systems and Software. ACM Computing Surveys, 34(2):171-210, June 2002.
3. R. Hartenstein. A Decade of Reconfigurable Computing: a Visionary Retrospective. In IEEE Design Automation and Test in Europe (DATE), Munich, Germany, March 2001.
4. Xilinx, http://www.xilinx.com.
5. Altera, http://www.altera.com.
6. S.C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R.R. Taylor. PipeRench: A Reconfigurable Architecture and Compiler. Computer: Innovative Technology for Computer Profesionals, 33(4):70-77, April 2000.
7. J. Becker, M. Glesner, A. Alsolaim, and J. Starzyk. Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures. In Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), Las Vegas, USA, June 2000.
8. H. Singh, M.-H. Lee, G. Lu, F.J. Kurdahi, N. Bagherzadeh, and E.M. Chaves Filho. MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. IEEE Trans. on Computers, Vol.49, No.5:465-481, May 2000.
9. T. Miyamori and K. Olukotun. REMARC: Reconfigurable Multimedia Array Coprocessor. In ACM/SIGDA Field Programmable Gate Array (FPGA), Monterey, USA, February 1998.
10. D. Cronquist. Architecture Design of Reconfigurable Pipelined Datapaths. In Advanced Research in VLSI (ARVLSI), Atlanta, USA, March 1999.
11. R. David, S. Pillement, and O. Sentieys. Low-Power Electronics Design, chapter 20: Low-Power Reconfigurable Processors. CRC press edited by C. Piguet, April 2004.
12. G. Sassateli, L. Torres, P. Benoit, T. Gil, G. Cambon, and J. Galy. Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP applications. In IEEE Design Automation and Test in Europe (DATE), Paris, France, March 2002.
13. G.M. Amdahl. Validity of the Single-Processor Approach to Achieving Large Scale Computing Capabilities. In AFIPS Conference Proceedings vol.30, Atlantic City, USA, April 1967.
14. J. Becker and M. Vorbach. Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC). In IEEE Computer Society Annual Workshop on VLSI (WVLSI), Florida, USA, February 2003.
15. Y. Chou, P. Pillai, H. Schmit, and J.P. Shen. PipeRench Implementation of the Instruction Path Coprocessor. In Symposium on Microarchitecture (MICRO-33), Monterey, USA, December 2000.
16. B. Mei, S. Vernalde, D. Verkest, and R. Lauwereins. Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. In Design Automation and Test in Europe (DATE), Paris, France, February 2004.
17. Z. Ye, P. Banerjee, S. Hauck, and A. Moshovos. CHIMAERA: A High-Performance Architecture with a Tightly-Coupled RFU. In the 27th Annual International Symposium on Computer Architecture (ISCA), Vancouver, Canada, June 2000.
18. C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale. The NAPA Adaptive Processing Architecture. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa Valley, USA, April 1998.
19. J.R. Hauser and J. Wawrzynek. GARP: A MIPS Processor with a Reconfigurable Coprocessor. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa Valley, USA, April 1997.
20. D. Rizzo and O. Colavin. A Video Compression Case Study on a Reconfigurable VLIW Architecture. In Design Automation and Test in Europe (DATE), Paris, France, March 2002.
21. S. Chevobbe, N. Ventroux, F. Blanc, and T. Collette. RAMPASS: Reconfigurable and Advanced Multi-Processing Architecture for future Silicon System. In 3rd International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2003.
22. G. Aigner, A. Diwan, D.L. Heine, M.S. Lam, D.L. Moore, B.R. Murphy, and C. Sapuntzakis. The Basic SUIF Programming Guide. Technical report, Computer Systems Laboratory, Stanford University, USA, August 2000.
23. M.D. Smith and G. Holloway. An Introduction to Machine SUIF and its Portable Libraries for Analysis and Optimization. Technical report, Division of Engineering and Applied Sciences, Harvard University, USA, July 2002.
24. I.E. Sutherland. Micropipelines. Communications of the ACM, 32(6):720-738, 1989.
25. J. Gerlach and W. Rosenstiel. System level design using the SystemC modeling platform. In the 3rd Workshop on System Design Automation (SDA), Rathen, Germany, 2000.
26. S. Swan. An Introduction to System Level Modeling in SystemC 2.0. Technical report, Cadence Design Systems, Inc., May 2001.
27. T. Zahariadis and D. Kalivas. A Spiral Search Algorithm for Fast Estimation of Block Motion Vectors. In the 8th European Signal Processing Conference (EUSIPCO), Trieste, Italy, September 1996.