Implicit parallelism with ordered transactions

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP

Volumn , Issue , 2007, Pages 79-89

  Von Praun, Christoph ^a   Ceze, Luis ^b   Cacaval, Calin ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b University of Illinois at Urbana Champaign

Author keywords

Implicit parallelism; Ordered transactions; Parallel programming; Program parallelization; Thread level speculation; Transactional memory

Indexed keywords

AUTOMATION; COMPUTER SOFTWARE; MATHEMATICAL MODELS; OPTIMIZATION; SCHEDULING; SEMANTICS;

IMPLICIT PARALLELISM; ORDERED TRANSACTIONS; PROGRAM PARALLELIZATION; THREAD-LEVEL SPECULATION;

PARALLEL PROGRAMMING;

EID: 34748925815     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1229428.1229443     Document Type: Conference Paper

References (32)

1. V. Aslot, M. Domeika, R. Eigenmann, G. Gaertner, W. B. Jones, and B. Parady. SPEComp: A new benchmark suite for measuring parallel computer performance. Lecture Notes in Computer Science, 2104, 2001.
2. S. Borkar. MICRO keynote talk, 2004.
3. B. D. Carlstrom, A. McDonald, H. Chafi, J. Chung, C. C. Minh, C. Kozyrakis, and K. Olukotun. The ATOMOE transactional programming language. In Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, June 2006.
4. P. Charles, C. Donawa, K. Ebcioglu, C. Grothoff, A. Kielstra, C. von Praun, V. Saraswat, and V. Sarkar. X10: An object-oriented approach, to non-uniform cluster computing. In Object-Oriented Programming, Systems, Languages, and Applications, Mar 2005.
5. P. A. Emrath and D. A. Padua. Automatic detection of nondeterminacy in parallel programs. In Proceedings of the ACM Workshop on Parallel and Distributed Debugging, pages 89-99, Jan. 1989.
6. C. Flanagan and S. Qadeer. A type and effect system for atomicity. In Proceedings of the 2003 Conference on Programming Language Design and Implementation, pages 338-349, Jun 2003.
7. S. Gopal, T. Vijaykumar, J. Smith, and G. Sohi. Speculative versioning cache. In Proceedings of the 4th International Symposium on High-Performance Computer Architecture, February 1998.
8. L. Hammond, B. Carlstrom, V. Wong, B. Hertzberg, M. Chen, C. Kozyrakis, and K. Olukotun. Programming with, transactional coherence and consistency (TCC). In Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, Oct 2004.
9. L. Hammond, M. Willey, and K. Olukotun. Data speculation support for a chip multiprocessor. In Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.
10. M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 289-300, May 1993.
11. T. A. Johnson, R. Eigenmann, and T. N. Vijaykumar. Min-cut program decomposition for thread-level speculation. In Proceedings of the ACM SIGPLAN 2004 Conference on Programming Languages Design and Implementation, June 2004.
12. L. Kale and S. Krishnan. CHARM++: A portable concurrent object oriented system based on C++. In Proceedings of the ACM Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA '93), pages 9.1-108, 1993.
13. A. Kejariwal, X. Tian, W. Li, M. Girkar, S. Kozhukhov, and H. Saito. On the performance potential of different types of speculative threadlevel parallelism. In Proceedings of the 20th Annual International conference on Supercomputing, June 2006.
14. G. Lee, C. P. Kruskal, and D. J. Kuck. An empirical study of automatic restructuring of non-numerical, programs for parallel processors. IEEE Transactions on Computers, 34(10):927-933, 1985.
15. W Liu, J. Tuck, L. Ceze, W. Ahn, K. Strauss, J. Renau, and J. Torrellas. Posh: A tls compiler that exploits program structure. In Proceedings of the Eleventh ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, March 2006.
16. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation, June 2005.
17. J. Manson, W Pugh, and S. Adve. The Java memory model. In Proceedings of the Symposium on Principles of Programming Languages (POPL'05), pages 378-391, 2005.
18. R. Netzer and B. Miller. What are race conditions? Some issues and formalizations. ACM Letters on Programming Languages and Systems, 1(1):74-88, Mar. 1992.
19. J. C. Phillips, G. Zheng, S. Kumar, and L. V. Kalé. NAMD: Biomolecular simulation on thousands of processors. In Proceedings of the 2002 ACM/EEE conference on Supercomputing, pages 1-18, Baltimore, MD, September 2002.
20. W. M. Pottenger. Induction variable substitution and reduction recognition in the Polaris parallelizing compiler. Master's thesis, Department of Computer Science. University of Illinois at UrbanaChampaign, December 1995.
21. M. K. Prabhu and K. Olukotun. Using thread-level speculation to simplify manual, parallelization. In Proceedings of the Ninth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, June 2003.
22. M. K. Prabhu and K. Olukotun. Exposing speculative thread parallelism in spec2000. In Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, June 2005.
23. W. Pugh. The Java memory model is fatally flawed. Concurrency: Practice and Experience, 12(6):445-455, 2000.
24. J. Rattner. PACT keynote talk, 2005.
25. J. Renau, J. Tuck, W. Liu, L. Ceze, K. Strauss, and J. Torrellas. Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation. In Proceedings of the 19th Annual International conference on Supercomputing, June 2005.
26. M. Rinard and M. Lam. The design, implementation and evaluation of Jade. ACM Transactions on Programming Languages and Systems, 20(3):483-545, May 1998.
27. G. S. Sohi, S. E. Breach, and T. N. Vijaykumar. Multiscalar processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.
28. J. Steffan, C. Colohan, A. Zhai, and T. Mowry. A scalable approach to thread-level speculation. In Proceedings of the 27th International Symposium on Computer Architecture, Jun 2000.
29. J. G. Steffan, C. B. Colohan, A. Zhai, and T. C. Mowry. Improving value communication for thread-level speculation. In International Symposium on High-Performance Computer Architecture (HPCA), pages 65-, 2002.
30. J. G. Steffan and T. C. Mowry. The potential for using thread-level data speculation to facilitate automatic parallelization. In HPCA, 1998.
31. The UMT benchmark code, http://www.llnl.gov/asci/purple/benchmarks/ limited/umt.
32. A. WeIc, S. Jagannathan, and A. Hosking. Safe futures for Java. In Proceedings of the ACM Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA'05), pages 439-453, 2005.