Improving value communication for thread-level speculation

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2002-January, Issue , 2002, Pages 65-75

  Steffan, J G ^a   Colohan, C B ^a   Zhai, A ^a   Mowry, T C ^a  

^a Carnegie Mellon University   (United States)

Author keywords

Application software; Computer science; Costs; Hardware; Microprocessors; Runtime; Sun; Throughput; Writing; Yarn

Indexed keywords

APPLICATION PROGRAMS; BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; COSTS; FORECASTING; HARDWARE; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; SEEBECK EFFECT; SUN; SUPERCOMPUTERS; SYNCHRONIZATION; TECHNICAL WRITING; THROUGHPUT; VALUE ENGINEERING; YARN;

HIGH COSTS; PARALLEL EXECUTIONS; PRIORITIZATION; RUNTIMES; THREAD LEVEL SPECULATION; VALUE PREDICTION;

COMPUTER HARDWARE;

EID: 84949785579     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2002.995699     Document Type: Conference Paper

References (38)

1. A. V. Aho, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques and Tools. Addison Wesley, 1986.
2. H. Akkary and M. Driscoll. A Dynamic Multithreading Processor. In MICRO-31, December 1998.
3. W. Blume, R. Doallo, R. Eigenmann, J. Grout, J. Hoeflinger, T. Lawrence, J. Lee, D. Padua, Y. Paek, B. Pottenger, L. Rauchwerger, and P. Tu. Parallel programming with polaris. IEEE Computer, 29(12):78-82, 1996.
4. B. Calder, G. Reinman, and D. Tullsen. Selective value prediction. In International Symposium on Computer Architecture, 1999.
5. G. Chrysos and J. Emer. Memory dependency prediction using store sets. June 1998.
6. M. Cintra, J. F. Martínez, and J. Torrellas. Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors. In Proceedings of ISCA 27, June 2000.
7. M. Cintra and J. Torrellas. Learning cross-thread violations in speculative parallelization for multiprocessors. In HPCA02, 2002.
8. Broadcom Corporation. The Sibyte SB-1250 Processor. http://www.sibyte.com/mercurian.
9. Standard Performance Evaluation Corporation. The SPEC Benchmark Suite. Technical report. http://www.spechbench.org.
10. R. Cytron. Doacross: Beyond vectorization for multiprocessors. In International Conference on Parallel Processing, 1986.
11. Brian A. Fields, Shai Rubin, and Rastislav Bodik. Focusing processor policies via critical-path prediction. In ISCA 2001, 2001.
12. M. Franklin and G. S. Sohi. ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. IEEE Transactions on Computers, 45(5), May 1996.
13. F. Gabbay and A. Mendelson. Speculative execution based on value prediction. Technical Report EE Department TR #1080, Technion-Israel Institute of Technology, 1996.
14. S. Gopal, T. Vijaykumar, J. Smith, and G. Sohi. Speculative Versioning Cache. In Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, February 1998.
15. M. Gupta and R. Nim. Techniques for Speculative Run-Time Parallelization of Loops. In Supercomputing '98, November 1998.
16. L. Hammond, M. Willey, and K. Olukotun. Data Speculation Support for a Chip Multiprocessor. In Proceedings of ASPLOS-VIII, October 1998.
17. Seema Hiranandani, Ken Kennedy, and Chau-Wen Tseng. Preliminary experiences with the Fortran D compiler. In Supercomputing '93, 1993.
18. J. Kahle. Power4: A Dual-CPU Processor Chip. Microprocessor Forum '99, October 1999.
19. Jens Knoop and Oliver Ruthing. Lazy code motion. In Proc. ACM SIGPLAN 92 Conference on Programming Language Design and Implementation, 92.
20. V. Krishnan and J. Torrellas. The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. In International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1999.
21. Kevin M. Lepak and Mikko H. Lipasti. On the value locality of store instructions. In Proceedings of ISCA 27, June 2000.
22. Mikko H. Lipasti and John Paul Shen. Exceeding the dataflow limit via value prediction. In International Symposium on Microarchitecture, 1996.
23. P. Marcuello and A. Gonzlez. Clustered Speculative Multithreaded Processors. In Proc. of the ACM Int. Conf. on Supercomputing, June 1999.
24. P. Marcuello, J. Tubella, and A. Gonzalez. Value prediction for speculative multithreaded architectures. In International Symposium on Microarchitecture, November 1999.
25. A. Moshovos, S. Breach, T. Vijaykumar, and G. Sohi. Dynamic speculation and synchronization of data dependences. June 1997.
26. J. Oplinger, D. Heine, and M. S. Lam. In Search of Speculative Thread-Level Parallelism. In Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT'99), October 1999.
27. D. Padua, D. Kuck, and D. Lawrie. High-speed multiprocessors and compilation techniques. IEEE Transactions on Computing, September 1980.
28. E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith. Trace processors. In Proceedings of Micro 30, 1997.
29. Y. Sazeides and J. E. Smith. The Predictability of Data Values. Proceedings of Micro 13, pages 248-258, December 1997.
30. G. S. Sohi, S. Breach, and T. N. Vijaykumar. Multiscalar Processors. In Proceedings of ISCA 22, pages 414-425, June 1995.
31. J. G. Steffan, C. B. Colohan, and T. C. Mowry. Architectural Support for Thread-Level Data Speculation. Technical Report CMU-CS-97-188, School of Computer Science, Carnegie Mellon University, November 1997.
32. J. G. Steffan, C. B. Colohan, A. Zhaia, and T. C. Mowry. A Scalable Approach to Thread-Level Speculation. In Proceedings of ISCA 27, June 2000.
33. S. Tjiang, M. Wolf, M. Lam, K. Pieper, and J. Hennessy. Languages and Compilers for Parallel Computing, pages 137-151. Springer-Verlag, Berlin, Germany, 1992.
34. M. Tremblay. MAJC: Microprocessor Architecture for Java Computing. HotChips '99, August 1999.
35. J.-Y. Tsai, J. Huang, C. Amlo, D.J. Lilja, and P.-C. Yew. The Superthreaded Processor Architecture. IEEE Transactions on Computers, Special Issue on Multithreaded Architectures, 48(9), September 1999.
36. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous Multithreading: Maximizing On-Chip Parallelism. In Proceedings of ISCA 22, pages 392-403, June 1995.
37. Kai Wang and Manoj Franklin. Highly accurate data value prediction using hybrid predictors. In International Symposium on Microarchitecture, 1997.
38. K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, April 1996.