-
1
-
-
0026901915
-
Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications
-
Aug
-
Lewis, S.H., "Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications", IEEE transactions on circuits and systems II: Analog and digital signal processing, Vol. 39, No. 8, Aug.1992, pp. 516-523
-
(1992)
IEEE transactions on circuits and systems II: Analog and digital signal processing
, vol.39
, Issue.8
, pp. 516-523
-
-
Lewis, S.H.1
-
2
-
-
0030106088
-
A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS
-
March
-
Cline, D.W.; Gray, P.R., "A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS", IEEE Journal of Solid-State Circuits, Volume: 31 , Issue: 3 , March 1996, pp. 294 - 303
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, Issue.3
, pp. 294-303
-
-
Cline, D.W.1
Gray, P.R.2
-
3
-
-
0026836960
-
A 10-b 20-MS/s analog-to-digital converter
-
Mar
-
S. H. Lewis et al., "A 10-b 20-MS/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 27, Mar. 1992. pp. 351-358
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 351-358
-
-
Lewis, S.H.1
-
4
-
-
0029269932
-
A 10 b 20 Msamples/s, 35mW pipeline A/D converter
-
Mar
-
T. Cho and P. Gray, "A 10 b 20 Msamples/s, 35mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, Mar.1995. pp. 166-172
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, pp. 166-172
-
-
Cho, T.1
Gray, P.2
-
5
-
-
0028749253
-
Design considerations for low-power, high-speed CMOS analog/digital converters, Low Power Electronics, 1994. Digest of Technical Papers
-
10-12 Oct
-
Cho, T.B.; Cline, D.W.; Conroy, C.S.G.; Gray, P.R., "Design considerations for low-power, high-speed CMOS analog/digital converters", Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium ,10-12 Oct. 1994 , pp. 70 - 73
-
(1994)
IEEE Symposium
, pp. 70-73
-
-
Cho, T.B.1
Cline, D.W.2
Conroy, C.S.G.3
Gray, P.R.4
-
6
-
-
0032259908
-
Systematic Design for Optimization of High-Speed Self-Calibrated Pipelined A/D Converters
-
Dec
-
J.Goes, J.Vital, J. E.Franca, "Systematic Design for Optimization of High-Speed Self-Calibrated Pipelined A/D Converters", IEEE transactions on circuits and systems II: Analog and digital signal processing, Vol. 45, No. 12, Dec.1998, pp. 1513-1526
-
(1998)
IEEE transactions on circuits and systems II: Analog and digital signal processing
, vol.45
, Issue.12
, pp. 1513-1526
-
-
Goes, J.1
Vital, J.2
Franca, J.E.3
-
7
-
-
0032626968
-
Power Optimization for Pipeline Analog-to-Digital Converters
-
May
-
Kwok, P.T. F. and Luong, Howard C, "Power Optimization for Pipeline Analog-to-Digital Converters", IEEE transactions on circuits and systems II: Analog and digital signal processing, Vol. 46, No. 5, May 1999, pp. 549-553
-
(1999)
IEEE transactions on circuits and systems II: Analog and digital signal processing
, vol.46
, Issue.5
, pp. 549-553
-
-
Kwok, P.T.F.1
Luong, H.C.2
-
8
-
-
0033872609
-
A 55-mW, 10-bit, 40-Msample/s Nyquistrate CMOS ADC
-
March 20000, pp
-
Mehr, I.; Singer, L., " A 55-mW, 10-bit, 40-Msample/s Nyquistrate CMOS ADC", IEEE Journal of Solid-State Circuits, Volume: 35 , Issue: 3 ,March 20000, pp. 318 - 325
-
IEEE Journal of Solid-State Circuits
, vol.35
, Issue.3
-
-
Mehr, I.1
Singer, L.2
-
9
-
-
67649116796
-
-
Chiang, Meei-Ling, U.S. application No. 09/506,284, filed Feb17, 2000, claims 1 to 27
-
Chiang, Meei-Ling, U.S. application No. 09/506,284, filed Feb17, 2000, claims 1 to 27
-
-
-
-
10
-
-
67649100493
-
-
Chiang, Meei-Ling, U.S. application No. 09/506,208, filed Feb17, 2000, claims 1 to 17
-
Chiang, Meei-Ling, U.S. application No. 09/506,208, filed Feb17, 2000, claims 1 to 17
-
-
-
-
11
-
-
0032664038
-
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
-
May
-
Abo, A.M.; Gray, P.R., "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter", IEEE Journal of Solid-State Circuits, Vol. 34 , Issue: 5 , May 1999, pp. 599 - 606
-
(1999)
IEEE Journal of Solid-State Circuits
, vol.34
, Issue.5
, pp. 599-606
-
-
Abo, A.M.1
Gray, P.R.2
-
12
-
-
0032073841
-
CMOS Charge-Transfer Preamplifer for Offset-Fluctuation Cancellationin Low-Power A/D conveters
-
Apr
-
K.Kotani, T.Shibata, and T.Ohmi, "CMOS Charge-Transfer Preamplifer for Offset-Fluctuation Cancellationin Low-Power A/D conveters", IEEE Journal of Solid-State Circuits, Vol. 24 , Issue: 2 , Apr.1998, pp. 241 - 249
-
(1998)
IEEE Journal of Solid-State Circuits
, vol.24
, Issue.2
, pp. 241-249
-
-
Kotani, K.1
Shibata, T.2
Ohmi, T.3
|