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Volumn , Issue , 2005, Pages 1968-1971

kT/C constrained optimization of power in pipeline ADCs

Author keywords

[No Author keywords available]

Indexed keywords

EFFECTIVE NUMBER OF BITS; KT/C NOISE; NEAR-OPTIMAL SOLUTIONS; PIPELINE ADC; PIPELINE ADCS; PIPELINED ADC; POWER CONSUMPTION; SCALING FUNCTIONS; TOTAL POWER;

EID: 34748889106     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465000     Document Type: Conference Paper
Times cited : (6)

References (12)
  • 1
    • 0026901915 scopus 로고
    • Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications
    • Aug
    • Lewis, S.H., "Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications", IEEE transactions on circuits and systems II: Analog and digital signal processing, Vol. 39, No. 8, Aug.1992, pp. 516-523
    • (1992) IEEE transactions on circuits and systems II: Analog and digital signal processing , vol.39 , Issue.8 , pp. 516-523
    • Lewis, S.H.1
  • 2
    • 0030106088 scopus 로고    scopus 로고
    • A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS
    • March
    • Cline, D.W.; Gray, P.R., "A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS", IEEE Journal of Solid-State Circuits, Volume: 31 , Issue: 3 , March 1996, pp. 294 - 303
    • (1996) IEEE Journal of Solid-State Circuits , vol.31 , Issue.3 , pp. 294-303
    • Cline, D.W.1    Gray, P.R.2
  • 3
    • 0026836960 scopus 로고
    • A 10-b 20-MS/s analog-to-digital converter
    • Mar
    • S. H. Lewis et al., "A 10-b 20-MS/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 27, Mar. 1992. pp. 351-358
    • (1992) IEEE J. Solid-State Circuits , vol.27 , pp. 351-358
    • Lewis, S.H.1
  • 4
    • 0029269932 scopus 로고
    • A 10 b 20 Msamples/s, 35mW pipeline A/D converter
    • Mar
    • T. Cho and P. Gray, "A 10 b 20 Msamples/s, 35mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, Mar.1995. pp. 166-172
    • (1995) IEEE J. Solid-State Circuits , vol.30 , pp. 166-172
    • Cho, T.1    Gray, P.2
  • 5
    • 0028749253 scopus 로고
    • Design considerations for low-power, high-speed CMOS analog/digital converters, Low Power Electronics, 1994. Digest of Technical Papers
    • 10-12 Oct
    • Cho, T.B.; Cline, D.W.; Conroy, C.S.G.; Gray, P.R., "Design considerations for low-power, high-speed CMOS analog/digital converters", Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium ,10-12 Oct. 1994 , pp. 70 - 73
    • (1994) IEEE Symposium , pp. 70-73
    • Cho, T.B.1    Cline, D.W.2    Conroy, C.S.G.3    Gray, P.R.4
  • 8
    • 0033872609 scopus 로고    scopus 로고
    • A 55-mW, 10-bit, 40-Msample/s Nyquistrate CMOS ADC
    • March 20000, pp
    • Mehr, I.; Singer, L., " A 55-mW, 10-bit, 40-Msample/s Nyquistrate CMOS ADC", IEEE Journal of Solid-State Circuits, Volume: 35 , Issue: 3 ,March 20000, pp. 318 - 325
    • IEEE Journal of Solid-State Circuits , vol.35 , Issue.3
    • Mehr, I.1    Singer, L.2
  • 9
    • 67649116796 scopus 로고    scopus 로고
    • Chiang, Meei-Ling, U.S. application No. 09/506,284, filed Feb17, 2000, claims 1 to 27
    • Chiang, Meei-Ling, U.S. application No. 09/506,284, filed Feb17, 2000, claims 1 to 27
  • 10
    • 67649100493 scopus 로고    scopus 로고
    • Chiang, Meei-Ling, U.S. application No. 09/506,208, filed Feb17, 2000, claims 1 to 17
    • Chiang, Meei-Ling, U.S. application No. 09/506,208, filed Feb17, 2000, claims 1 to 17
  • 11
    • 0032664038 scopus 로고    scopus 로고
    • A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
    • May
    • Abo, A.M.; Gray, P.R., "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter", IEEE Journal of Solid-State Circuits, Vol. 34 , Issue: 5 , May 1999, pp. 599 - 606
    • (1999) IEEE Journal of Solid-State Circuits , vol.34 , Issue.5 , pp. 599-606
    • Abo, A.M.1    Gray, P.R.2
  • 12
    • 0032073841 scopus 로고    scopus 로고
    • CMOS Charge-Transfer Preamplifer for Offset-Fluctuation Cancellationin Low-Power A/D conveters
    • Apr
    • K.Kotani, T.Shibata, and T.Ohmi, "CMOS Charge-Transfer Preamplifer for Offset-Fluctuation Cancellationin Low-Power A/D conveters", IEEE Journal of Solid-State Circuits, Vol. 24 , Issue: 2 , Apr.1998, pp. 241 - 249
    • (1998) IEEE Journal of Solid-State Circuits , vol.24 , Issue.2 , pp. 241-249
    • Kotani, K.1    Shibata, T.2    Ohmi, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.