A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 10, 2007, Pages 2149-2160

  Lee, Zwei Mei ^a,b   Wang, Cheng Yeh ^a,b   Wu, Jieh Tsorng ^a,b  

^a IEEE

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Analog digital conversion; Calibration; Sample and hold circuits

Indexed keywords

ANALOG TO DIGITAL CONVERSION; ELECTRIC POWER SYSTEMS; ENERGY DISSIPATION; GAIN CONTROL; OPERATIONAL AMPLIFIERS; POWER CONVERTERS;

CONVERSION LINEARITY; DIGITAL BACKGROUND CALIBRATION; OPAMP; TIME-INTERLEAVED ADC;

CMOS INTEGRATED CIRCUITS;

EID: 34748862291     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.905293     Document Type: Conference Paper

References (14)

1. P. Bogner, F. Kuttner, C. Kropf, T. Hartig, M. Burian, and H. Eul, "A 14b 100 MS/s digitally self-calibrated pipelined ADC in 0.13 μm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San. Francisco, CA, Feb. 2006, vol. 650, pp. 224-225.
2. H.-C. Liu, Z.-M. Lee, and J. Wu, "A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1047-1056, May 2005.
3. E. Siragusa and I. Galten, "A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2126-2138, Dec. 2004.
4. J. William, C. Black, and D. A. Hodges, "Time interleaved converter arrays," IEEE J. Solid-State Circuits, vol. SC-15, no. 12, pp. 1022-1028, Dec. 1980.
5. S. M. Jamal, D. Fu, N. C-J. Chang, P. J. Hurst, and S. H. Lewis, "A 10-bit 120 MSample/s time-interleaved analog-to-digital converter with digital background calibration," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1618-1627, Dec. 2002.
6. J. Elbornsson, F. Gustafsson, and J.-E. Eklund, "Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 151-158, Jan. 2004.
7. C.-C. Hsu and J.-T. Wu, "A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier," IEICE Trans. Electron., vol. E86-C, pp. 2122-2128, Oct. 2003.
8. A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
9. P. J. Hurst, S. H. Lewis, J. P. Keane, F. Aram, and K. C. Dyer, "Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 51, no. 2, pp. 275-285, Feb. 2004.
10. G. S. Ostrem, O. Moldsvor, and A. O. Aaserud, "A compact 3 V, 70 m.W, 12-bit video-speed CMOS ADC," Analog Integr. Circuits Signal Process., vol. 15, pp. 27-36, Jan. 1998.
11. K. Gulati and H.-S. Lee, "A low-power reconfigurable analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1900-1911, Dec. 2001.
12. M. Shinagawa, Y. Akazawa, and T. Wakimoto, "Jitter analysis of high-speed sampling systems," IEEE J. Solid-State. Circuits, vol. 25, no. 2, pp. 220-224, Feb. 1990.
13. A. M. Ali, C. D. Sneed, R. Sneed, A. Morgan, J. Kornblum, L. Wu, and S. Bardsley, "A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter," in. Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2005, pp. 10-4-1-10-4-4.
14. V. Hakkarainen, M. Aho, L. Sumanen, M. Waltari, and K. Halonen, "A 14b 200 MHz IF-sampling A/D converter with 79.9 dB SFDR," in Proc. IEEE Norchip Conf., Oslo, Norway, Nov. 2004, pp. 171-174.