-
3
-
-
0029388575
-
A high-speed realization of residue to binary system converter
-
Oct.
-
S. J. Piestrak, “A high-speed realization of residue to binary system converter,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 10, pp. 661–663, Oct. 1995.
-
(1995)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.42
, Issue.10
, pp. 661-663
-
-
Piestrak, S.J.1
-
4
-
-
28244477506
-
Comments on ‘A high-speed realization of a residue to binary number system converter
-
Mar.
-
A. Dhurkadas, “Comments on ‘A high-speed realization of a residue to binary number system converter’,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 3, pp. 446–447, Mar. 1998.
-
(1998)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.45
, Issue.3
, pp. 446-447
-
-
Dhurkadas, A.1
-
5
-
-
0032155165
-
n+ 1}-moduli set
-
Sep.
-
n+ 1}-moduli set,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 9, pp. 998–1002, Sep. 1998.
-
(1998)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl
, vol.45
, Issue.9
, pp. 998-1002
-
-
Bharadwaj, M.1
Premkumar, A.B.2
Srikanthan, T.3
-
6
-
-
0036648036
-
n+ 1}
-
Jul.
-
n+ 1},” IEEE Trans. Signal Processing, vol. 50, no. 7, pp. 1772–1779, Jul. 2002.
-
(2002)
IEEE Trans. Signal Processing
, vol.50
, Issue.7
, pp. 1772-1779
-
-
Wang, Y.1
Song, X.2
Aboulhamid, M.3
Shen, H.4
-
7
-
-
0032000038
-
k-1- 1}
-
Feb.
-
k-1- 1},” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 2, pp. 204–209, Feb. 1998.
-
(1998)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.45
, Issue.2
, pp. 204-209
-
-
Hiasat, A.A.1
Abdel-Aty-Zohdy, H.S.2
-
8
-
-
0034460249
-
k-1- 1} RNS and a scheme for its VLSI implementation
-
Dec.
-
k-1- 1} RNS and a scheme for its VLSI implementation,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 12, pp. 1576–1581, Dec. 2000.
-
(2000)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.47
, Issue.12
, pp. 1576-1581
-
-
Wang, W.1
Swamy, M.N.S.2
Ahmad, M.O.3
Wang, Y.4
-
10
-
-
0028463884
-
k- 1 adder design
-
k- 1 adder design,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 41, pp. 463–466, 1994.
-
(1994)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.41
, pp. 463-466
-
-
Efstathiou, C.1
Nikolos, D.2
Kalamatinos, J.3
-
11
-
-
0037301573
-
A study of the residue-to-binary converters for the three-moduli sets
-
Feb.
-
W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, “A study of the residue-to-binary converters for the three-moduli sets,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 2, p., Feb. 2003.
-
(2003)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.
, vol.50
, Issue.2
-
-
Wang, W.1
Swamy, M.N.S.2
Ahmad, M.O.3
Wang, Y.4
-
12
-
-
24944514297
-
n+1- 1}
-
Sep.
-
n+1- 1},” Proc. IEE Comput. Digit. Tech., vol. 152, no. 5, pp. 687–696, Sep. 2005.
-
(2005)
Proc. IEE Comput. Digit. Tech.
, vol.152
, Issue.5
, pp. 687-696
-
-
Cao, B.1
Srikanthan, T.2
Chang, C.H.3
-
14
-
-
0024072353
-
Fast conversion between binary and residue numbers
-
Sep.
-
G. Bi and E. V. Jones, “Fast conversion between binary and residue numbers,” Electron. Lett., vol. 24, pp. 1195–1197, Sep. 1988.
-
(1988)
Electron. Lett.
, vol.24
, pp. 1195-1197
-
-
Bi, G.1
Jones, E.V.2
-
17
-
-
0036489983
-
k-1- 1} RNS and a scheme for its VLSI implementation'
-
Mar.
-
k-1- 1} RNS and a scheme for its VLSI implementation’,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 3, p. 230, Mar. 2002.
-
(2002)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.49
, Issue.3
, pp. 230
-
-
Wang, W.1
Swamy, M.N.S.2
Ahmad, M.O.3
Wang, Y.4
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