Comments on a high speed realization of a residue to binary number system converter

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 45, Issue 3, 1998, Pages 446-447

  Dhurkadas, A ^a  

^a NAVAL PHYSICAL AND OCEANOGRAPHIC LABORATORY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28244477506     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.664260     Document Type: Article

References (2)

1. S. J. Piestrak, A high speed realization of a residue to binary number system converter, IEEE Trans. Circuits Systems Analog Digital Signal Processing, pp. 661-663, Oct. 1995.
2. S. Andraos and H. Ahmad, A new efficient memoryless residue to binary converter, IEEE Trans. Circuits Systems, pp. 1441-1444, Nov. 1988.