Low-power embedded SRAM with the current-mode write technique

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 1, 2000, Pages 119-124

  Wang, Jinn Shyan ^a   Tseng, Wayne ^a   Li, Hung Yu ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC LOSSES; ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT;

CURRENT-MODE WRITE TECHNIQUES; STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0033908207     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.818929     Document Type: Article

References (7)

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3. T. N. Blalock and R. C. Jaeger, "A high-speed clamped bit-line current-mode sense amplifier," IEEE J. Solid-State Circuits, vol. 26, pp. 542-548, Apr. 1991.
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5. E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, pp. 748-754, Oct. 1987.
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7. "0.6-μm CMOS ASIC process digests," Taiwan Semiconductor Manufacture Corp., 1996.