A fast 3D-BSG algorithm for 3D packing problem

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2044-2047

  Zhang, Lingyi ^a   Dong, Sheqin ^a   Hong, Xianlong ^a   Ma, Yuchun ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GRAPH THEORY; LOGIC DESIGN;

BLOCK RELATION GRAPHS; FLOORPLAN DESIGN; FPGA DESIGN;

VLSI CIRCUITS;

EID: 34548855088     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378499     Document Type: Conference Paper

References (11)

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2. Hiroyuki Yamazaki, Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani, "The 3D-Packing by Meta Data structure and packing heuristics", IEICE Trans. Fundamentals, Vol.E83-A, No.4 April 2000.
3. Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen, "Temporal floorplanning using 3D-subTCG", Proc. ASPDAC, pp. 723-728, 2004
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8. Silke Salewski, Erich Barke, "An Upper Bound for 3D Slicing Floorplans" Proceeding of the 15th International Conference on VLSI Design, 2002
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