Optimization of dynamic hardware reconfigurations

Journal of Supercomputing

Volumn 19, Issue 1, 2001, Pages 57-75

  Teich, Jürgen ^a   Fekete, Sándor P ^b   Schepers, Jörg ^c  

^a UNIVERSITY OF PADERBORN   (Germany)

^b TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

^c IBM   (Germany)

Author keywords

Multi dimensional placement and packing; Reconfigurable hardware

Indexed keywords

ALGORITHMS; CHIP SCALE PACKAGES; COMPUTATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS; STATIC RANDOM ACCESS STORAGE;

DYNAMIC HARDWARE RECONFIGURATION;

COMPUTER HARDWARE;

EID: 0035338121     PISSN: 09208542     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1011188411132     Document Type: Article

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