An upper bound for 3D slicing floorplans

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 567-572

  Salewski, S ^a   Barke, E ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; COMPUTER AIDED DESIGN; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3D LAYOUTS; CHIP AREAS; DEEP SUB-MICRON DESIGNS; FLOOR-PLANNING; RESEARCH ACTIVITIES; SLICING FLOORPLANS; SLICING STRUCTURE; UPPER BOUND;

DESIGN;

EID: 84962222175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994982     Document Type: Conference Paper

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