메뉴 건너뛰기




Volumn , Issue , 2005, Pages 1960-1963

A new ratio-independent A/D conversion technique for high-resolution pipeline A/D converters

Author keywords

[No Author keywords available]

Indexed keywords

A/D CONVERSION; ANALOG-TO-DIGITAL; CAPACITOR MISMATCH ERRORS; HIGH RESOLUTION; OFFSET VOLTAGE; PIPELINE A/D CONVERTER; POWER CONSUMPTION;

EID: 34548853838     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464998     Document Type: Conference Paper
Times cited : (7)

References (10)
  • 1
    • 0024122160 scopus 로고
    • A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter
    • Dec
    • B.-S. Song, M.F. Tompsett, and K.R. Lakshmikumar, "A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter", IEEE J. Solid-State Circuits, vol. 23, pp. 1324-1333, Dec. 1988.
    • (1988) IEEE J. Solid-State Circuits , vol.23 , pp. 1324-1333
    • Song, B.-S.1    Tompsett, M.F.2    Lakshmikumar, K.R.3
  • 2
    • 0021598441 scopus 로고
    • A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique
    • December
    • P.W. Li, M.J. chin, P.R. Gray, and R. Castello, "A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique", IEEE J. Solid-State Circuits, vol. 19, pp. 828-836, December 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.19 , pp. 828-836
    • Li, P.W.1    chin, M.J.2    Gray, P.R.3    Castello, R.4
  • 3
    • 0031078998 scopus 로고    scopus 로고
    • Background Digital Calibration Techniques for Pipelined ADC's
    • February
    • U.-K. Moon and B.-S. Song, "Background Digital Calibration Techniques for Pipelined ADC's ", IEEE J. Solid-State Circuits, vol. 44, pp. 102-109, February. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.44 , pp. 102-109
    • Moon, U.-K.1    Song, B.-S.2
  • 4
    • 0032313025 scopus 로고    scopus 로고
    • A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters
    • December
    • D. Fu, K.C. Dyer, S.H. Lewis, and P.J. Hurst, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters",IEEE J. Solid-State Circuits, vol. 33, pp. 1904-1911, December. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , pp. 1904-1911
    • Fu, D.1    Dyer, K.C.2    Lewis, S.H.3    Hurst, P.J.4
  • 5
    • 0036612580 scopus 로고    scopus 로고
    • A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined A/D converter
    • December
    • S.-Y. Chuang, and T.L. Sculley, "A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined A/D converter", IEEE J. Solid-State Circuits, vol. 37, pp. 674-683, December. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , pp. 674-683
    • Chuang, S.-Y.1    Sculley, T.L.2
  • 7
    • 0033890089 scopus 로고    scopus 로고
    • Inherently Linear Capacitor Error-Averaging Technique for Pipeline A/D Conversion
    • March
    • Yun. Chiu, "Inherently Linear Capacitor Error-Averaging Technique for Pipeline A/D Conversion", IEEE Trans. Circuits Syst. II, vol. 47, pp. 229-232, March. 2000.
    • (2000) IEEE Trans. Circuits Syst. II , vol.47 , pp. 229-232
  • 8
    • 0030414371 scopus 로고    scopus 로고
    • A 2.5-V, 12-b, 5-MSample/s Pipelined CMOS ADC
    • December
    • P.C. Yu, and H.-S. Lee, "A 2.5-V, 12-b, 5-MSample/s Pipelined CMOS ADC", IEEE J. Solid-State Circuits, vol. 31, pp. 1854-1861, December. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 1854-1861
    • Yu, P.C.1    Lee, H.-S.2
  • 10
    • 0025568946 scopus 로고
    • A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
    • December
    • K. Bult and G.J.G.M. Geelen, "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain", IEEE J. Solid-State Circuits, vol. 25, pp. 1379-1384, December. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.25 , pp. 1379-1384
    • Bult, K.1    Geelen, G.J.G.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.