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Volumn , Issue , 2006, Pages 111-114

A versatile multimedia functional unit design using the spurious power suppression technique

Author keywords

Low power; Multimedia; Versatile; VLSI design

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; INTERPOLATION;

EID: 34250834462     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2006.357864     Document Type: Conference Paper
Times cited : (14)

References (6)
  • 1
    • 34250772314 scopus 로고    scopus 로고
    • Design Exploration of A Spurious Power Suppression Technique (SPST) and Its Applications
    • Hsinchu, Taiwan, Nov. 1-3
    • K. H. Chen, K. C. Chao, J. I. Guo, J. S. Wang, and Y. S. Chu, "Design Exploration of A Spurious Power Suppression Technique (SPST) and Its Applications," IEEE Asian Solid-State Circuits Conf, pp. 341-344, Hsinchu, Taiwan, Nov. 1-3, 2005.
    • (2005) IEEE Asian Solid-State Circuits Conf , pp. 341-344
    • Chen, K.H.1    Chao, K.C.2    Guo, J.I.3    Wang, J.S.4    Chu, Y.S.5
  • 2
    • 0042420597 scopus 로고    scopus 로고
    • Minimization of switching activities of partial products for designing low-power multipliers
    • June
    • O. Chen, S. Wang, and Y. W. Wu, "Minimization of switching activities of partial products for designing low-power multipliers," IEEE Trans. VLSI, vol. 11, no. 3, pp. 418-433, June, 2003.
    • (2003) IEEE Trans. VLSI , vol.11 , Issue.3 , pp. 418-433
    • Chen, O.1    Wang, S.2    Wu, Y.W.3
  • 3
    • 13844299623 scopus 로고    scopus 로고
    • A micropower low-voltage multiplier with reduced spurious switching
    • Feb
    • K. S. Chong, B. H. Gwee, and J. Chang, "A micropower low-voltage multiplier with reduced spurious switching," IEEE Trans. VLSI, vol. 13, no. 2, pp. 255-265, Feb. 2005.
    • (2005) IEEE Trans. VLSI , vol.13 , Issue.2 , pp. 255-265
    • Chong, K.S.1    Gwee, B.H.2    Chang, J.3
  • 4
    • 0038306218 scopus 로고    scopus 로고
    • A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL
    • Feb
    • H. H. Chang, S. H. Sun, and S. I. Liu, "A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL," IEEE Int. Solid-State Circuits Conf, vol. 1, pp. 434-505, Feb. 2003.
    • (2003) IEEE Int. Solid-State Circuits Conf , vol.1 , pp. 434-505
    • Chang, H.H.1    Sun, S.H.2    Liu, S.I.3
  • 5
    • 0035333219 scopus 로고    scopus 로고
    • A dual-loop delay-locked loop using multiple voltage-controlled delay lines
    • May
    • Y. J. Jung, S. W. Lee, D. Shim, W. Kim, C. Kim, and S. I. Cho, "A dual-loop delay-locked loop using multiple voltage-controlled delay lines," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 784-791, May 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.5 , pp. 784-791
    • Jung, Y.J.1    Lee, S.W.2    Shim, D.3    Kim, W.4    Kim, C.5    Cho, S.I.6
  • 6
    • 34250866695 scopus 로고    scopus 로고
    • Artisan component, TSMC 0.18-um process 1.8-volt SAGE-X standard cell library Data book, Sept. 2003.
    • Artisan component, "TSMC 0.18-um process 1.8-volt SAGE-X standard cell library Data book," Sept. 2003.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.