SCOPUS 정보 검색 플랫폼

Electronics Letters

Volumn 41, Issue 10, 2005, Pages 581-583

Low-power parallel multiplier with column bypassing

(3) Wen, M C a Wang, S J a Lin, Y N a

a NATIONAL CHUNG HSING UNIVERSITY (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRIC CURRENTS; ELECTRIC SWITCHES; FAST FOURIER TRANSFORMS; GATES (TRANSISTOR); LOGIC CIRCUITS; SWITCHING;

COLUMN BYPASSING; LOW-POWER DSP SYSTEMS; LOW-POWER PARALLEL MULTIPLIER; POWER DISSIPATION; POWER REDUCTION;

FREQUENCY MULTIPLYING CIRCUITS;

EID: 19944391581 PISSN: 00135194 EISSN: None Source Type: Journal
DOI: 10.1049/el:20050464 Document Type: Article

Times cited : (46)

References (3)

1
- 0029716111
- High performance adder cell for low power pipelined multiplier
- May
- Wu, A.: 'High performance adder cell for low power pipelined multiplier'. Proc. IEEE Int. Symp. on Circuits and Systems, May 1996, Vol. 4, pp. 57-60
- (1996) Proc. IEEE Int. Symp. on Circuits and Systems , vol.4 , pp. 57-60
- Wu, A.¹

2
- 0345471798
- Multiplier energy reduction through bypassing of partial products
- Ohban, J., Moshnyaga, V.G., and Inoue, K.: 'Multiplier energy reduction through bypassing of partial products'. Proc. Asia-Pacific Conf. on Circuits and Systems, 2002, Vol. 2, pp. 13-17
- (2002) Proc. Asia-pacific Conf. on Circuits and Systems , vol.2 , pp. 13-17
- Ohban, J.¹ Moshnyaga, V.G.² Inoue, K.³

3
- 0030269438
- Circuit techniques for CMOS low-power high-performance multipliers
- Abu-Khater, I.S., Bellaouar, A., and Elmasry, M.: 'Circuit techniques for CMOS low-power high-performance multipliers', IEEE J. Solid-State Circuits, 1996, 31, (10), pp. 1535-1546
- (1996) IEEE J. Solid-state Circuits , vol.31 , Issue.10 , pp. 1535-1546
- Abu-Khater, I.S.¹ Bellaouar, A.² Elmasry, M.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.