Acceleration of SAT-based iterative property checking

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3725 LNCS, Issue , 2005, Pages 349-353

  Große, Daniel ^a   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SCIENCE; COMPUTER SOFTWARE REUSABILITY; FORMAL LANGUAGES; OPTIMIZATION; PROBLEM SOLVING;

ITERATIVE PROPERTY; PROOFS ASSUMPTIONS; TEMPORAL PROPERTY;

ITERATIVE METHODS;

EID: 33646420863     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11560548_29     Document Type: Conference Paper

References (5)

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2. D. Große and R. Drechsler. CheckSyC: An efficient property checker for RTL SystemC designs, pages 4167-4170, 2005.
3. M.W. Moskewicz, C.F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Design Automation Conf., pages 530-535, 2001.
4. Ofer Shtrichman. Pruning techniques for the SAT-based bounded model checking problem, pages 58-70, 2001.
5. K. Winkelmann, H.-J. Trylus, D. Stoffel, and G. Fey. A cost-efficient block verification for a UMTS up-link chip-rate coprocessor. In Design, Automation and Test in Europe, volume 1, pages 162-167, 2004.