-
2
-
-
33646922057
-
The future of wires
-
Apr
-
R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, no. 4, pp. 490-504, Apr 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.4
, pp. 490-504
-
-
Ho, R.1
Mai, K.W.2
Horowitz, M.A.3
-
4
-
-
0033724253
-
Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor
-
Apr.
-
R. McInerney, et al., "Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor," ISPD Proc., pp. 99-104, Apr. 2000.
-
(2000)
ISPD Proc.
, pp. 99-104
-
-
McInerney, R.1
-
5
-
-
0000090413
-
An interconnect-centric design flow for nanometer technologies
-
Apr
-
J. Cong, "An interconnect-centric design flow for nanometer technologies," Proc. of the IEEE, vol. 89, no. 4, pp. 505-528, Apr 2001.
-
(2001)
Proc. of the IEEE
, vol.89
, Issue.4
, pp. 505-528
-
-
Cong, J.1
-
6
-
-
0042134692
-
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
-
Jun
-
R. Bashirullah, W. Liu, and R. Cavin, "Low-power design methodology for an on-chip bus with adaptive bandwidth capability," DAC, pp. 628-633, Jun 2003.
-
(2003)
DAC
, pp. 628-633
-
-
Bashirullah, R.1
Liu, W.2
Cavin, R.3
-
7
-
-
4544298460
-
A 16Gb/s adaptive banwidth on-chip bus based on hybrid current/voltage mode signaling
-
Jun
-
R. Bashirullah, et al., "A 16Gb/s adaptive banwidth on-chip bus based on hybrid current/voltage mode signaling," Symp. VLSI Circuits, pp. 392-393, Jun 2004.
-
(2004)
Symp. VLSI Circuits
, pp. 392-393
-
-
Bashirullah, R.1
-
8
-
-
28144463691
-
A 3Gb/s/ch transceiver for RC-limited on-chip interconnects
-
Feb
-
D. Schinkel, et al., "A 3Gb/s/ch transceiver for RC-limited on-chip interconnects," ISSCC, pp. 386-387, Feb 2005.
-
(2005)
ISSCC
, pp. 386-387
-
-
Schinkel, D.1
-
9
-
-
0141538149
-
Efficient on-chip global interconnects
-
Jun
-
R. Ho, K, Mai, and M. Horowitz, "Efficient on-chip global interconnects," Symp. VLSI Circuits, pp. 271-274, Jun 2003.
-
(2003)
Symp. VLSI Circuits
, pp. 271-274
-
-
Ho, R.1
Mai, K.2
Horowitz, M.3
-
11
-
-
0026141225
-
Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's
-
April
-
E. Seevinck, P. van Beers, and H. Ontrop, "Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 525-536, April 1991.
-
(1991)
IEEE J. Solid-state Circuits
, vol.26
, Issue.4
, pp. 525-536
-
-
Seevinck, E.1
Van Beers, P.2
Ontrop, H.3
-
12
-
-
0036866915
-
A power-optimal repeater insertion methodology for global interconnects in nanometer designs
-
Nov
-
K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 2001-2007, Nov 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.11
, pp. 2001-2007
-
-
Banerjee, K.1
Mehrotra, A.2
-
13
-
-
84861275958
-
-
http://www.oea.com/document/metal.pdf
-
-
-
-
14
-
-
0242526943
-
Static pulsed bus for on-chip interconnects
-
Jun
-
M. Khellah, J. Tschanz, Y. Ye, S. Narendra, and V. De, "Static pulsed bus for on-chip interconnects," Symp. VLSI Circuits, pp. 78-79, Jun 2002.
-
(2002)
Symp. VLSI Circuits
, pp. 78-79
-
-
Khellah, M.1
Tschanz, J.2
Ye, Y.3
Narendra, S.4
De, V.5
-
15
-
-
0035509997
-
Power-driven challenges in nanometer design
-
Nov
-
D. Sylvester and H. Kaul, "Power-driven challenges in nanometer design," IEEE Design & Test of Computers, vol. 18, issue. 6, pp. 12-21, Nov 2001.
-
(2001)
IEEE Design & Test of Computers
, vol.18
, Issue.6
, pp. 12-21
-
-
Sylvester, D.1
Kaul, H.2
-
16
-
-
0033704034
-
Low-swing on-chip signaling techniques: Effectiveness and robustness
-
Jun
-
H. Zhang, V. George, and M. Rabaey, "Low-swing on-chip signaling techniques: effectiveness and robustness," IEEE Trans. VLSI, vol. 8, no. 3, pp. 264-272, Jun 2000.
-
(2000)
IEEE Trans. VLSI
, vol.8
, Issue.3
, pp. 264-272
-
-
Zhang, H.1
George, V.2
Rabaey, M.3
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