The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications

IEEE Transactions on Electron Devices

Volumn 52, Issue 2, 2005, Pages 218-226

  Venkatraman, Ramnath ^a   Castagnetti, Ruggero ^a   Kobozeva, Olga ^a   Duan, Franklin L ^a   Kamath, Arvind ^a   Sabbagh, S T ^a   Vilchis Cruz, Miguel A ^a   Liaw, Jhon Jhy ^b   You, Jyh Cheng ^b   Ramesh, Subramanian ^a  

^a AGERE SYSTEMS   (United States)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Application specific integrated circuits (ASIC); MOS memory integrated circuits; Optical proximity correction (OPC); Semiconductor device reliability; Semiconductor process; Soft error rate (SER); Static noise margin (SNM); Static random access memory (SRAM); System on chip (SoC)

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; MONTE CARLO METHODS; RELIABILITY; SEMICONDUCTING SILICON;

MOS MEMORY INTEGRATED CIRCUITS; OPTICAL PROXIMITY CORRECTION (OPC); SEMICONDUCTOR DEVICE RELIABILITY; SEMICONDUCTOR PROCESS; SOFT ERROR RATE (SER); STATIC NOISE MARGIN (SNM); SYSTEM-ON-CHIP (SOC);

STATIC RANDOM ACCESS STORAGE;

EID: 19944430414     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.841346     Document Type: Article

References (10)

1. SIA International Technology Roadmap for Semiconductors, San Jose, CA, 2000.
2. W. Kong, R. Venkatraman, R. Castagnetti, F. Duan, and S. Ramesh, "High-density and high-performance 6T-SRAM for System-on-Chip in 130-nm CMOS technology," in Symp. VLSI Tech. Dig., 2001, p. 105.
3. F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, and S. Ramesh, "Design and use of memory-specific test structures to ensure SRAM yield and manufacturability," in Proc. Int. Symp. Quality Electronic Design, 2003, pp. 119-124.
4. S. Thompson, M. Alavi, M. Hussein, P. Jacob, C. Kenyon, P. Moon, M. Prince, S. Sivakumar, S. Tyagi, and M. Bohr, "130-nm logic technology featuring 60-nm transistors, low-Κ dielectrics and Cu interconnects," Intel Technol. J., vol. 6, pp. 5-13, 2002.
5. L. K. Han, S. Biesemans, J. Heidenreich, K. Houlihan, C. Lin, V. McGahay, T. Schiml, A. Schmidt, U. P. Schroeder, M. Stetter, C. Wann, D. Warner, R. Mahnkopf, and B. Chen, "A modular 0.13 μm bulk CMOS technology for high-performance and low power applications," in Symp. VLSI Tech. Dig., 2000, pp. 12-13.
6. K. K. Young, S. Y. Wu, C. C. Wu, C. H. Wang, C. T. Lin, J. Y. Cheng, M. Chiang, S. H. Chen, T. C. Lo, Y. S. Chen, J. H. Chen, L. J. Chen, S. Y. Hou, J. J. Liaw, T. E. Chang, C. S. Hou, J. Shih, S. M. Jeng, H. C. Hsieh, Y. Ku, T. Yen, H. Tao, L. C. Chao, S. Shue, S. M. Jang, T. C. Ong, C. H. Yu, M. S. Liang, C. H. Diaz, and J. Y. C. Sun, "A 0.13 μm CMOS technology with 193-nm lithography and Cu/Low-Κ for high-performance applications," in IEDM Tech. Dig., 2000, pp. 563-566.
7. O. Kobozeva, R. Venkatraman, R. Castagnetti, F. Duan, A. Kamath, and S. Ramesh. Designing high-performance cost-efficient embedded SRAM in deep submicron era. presented at SPIE 29th Annu. Int. Symp. Microlithography
8. E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. 22, pp. 748-754, 1987.
9. H. Puchner, Y.-C. Liu, W. Kong, F. Duan, and R. Castagnetti, " Substrate engineering to improve soft-error-rate immunity for SRAM technologies," Microelectron. Reliabil., vol. 41, pp. 1319-1324, 2001.
10. R. Baumann, "The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction," in IEDM Tech. Dig., 2002, pp. 329-332.