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Volumn , Issue , 2007, Pages 69-74

Communication-centric SoC debug using transactions

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; ERROR ANALYSIS; INTEGRATED CIRCUIT TESTING; PROGRAM DEBUGGING; PROGRAMMABLE LOGIC CONTROLLERS;

EID: 34548754565     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2007.14     Document Type: Conference Paper
Times cited : (7)

References (20)
  • 1
    • 33745582290 scopus 로고    scopus 로고
    • A new vision of 'scalable' verification
    • Mar
    • B. Bailey, "A new vision of 'scalable' verification," EETimes, Mar. 2004.
    • (2004) EETimes
    • Bailey, B.1
  • 3
    • 27844542862 scopus 로고    scopus 로고
    • An embedded debugging architecture for SoCs
    • Feb-Mar
    • R. Leatherman and N. Stollon, "An embedded debugging architecture for SoCs," IEEE Potentials, vol. 24, no. 1, pp. 12-16, Feb-Mar 2005.
    • (2005) IEEE Potentials , vol.24 , Issue.1 , pp. 12-16
    • Leatherman, R.1    Stollon, N.2
  • 11
    • 0036446214 scopus 로고    scopus 로고
    • Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips
    • Oct
    • S. K. Goel and B. Vermeulen, "Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips," in Proceedings IEEE International Test Conference (ITC), Oct. 2002, pp. 1103-1110.
    • (2002) Proceedings IEEE International Test Conference (ITC) , pp. 1103-1110
    • Goel, S.K.1    Vermeulen, B.2
  • 13
    • 15744374564 scopus 로고    scopus 로고
    • Transaction level modeling: Verification leaps ahead
    • Mar
    • B. Tabbara and K. Hashmi, "Transaction level modeling: Verification leaps ahead," EDA Tech Forum, pp. 14-17, Mar. 2005.
    • (2005) EDA Tech Forum , pp. 14-17
    • Tabbara, B.1    Hashmi, K.2
  • 18
    • 27344456043 scopus 로고    scopus 로고
    • The Æthereal network on chip: Concepts, architectures, and implementations
    • Sept-Oct
    • K. Goossens, J. Dielissen, and A. Rǎdulescu, "The Æthereal network on chip: Concepts, architectures, and implementations," IEEE Design and Test of Computers, vol. 22, no. 5, pp. 414-421, Sept-Oct 2005.
    • (2005) IEEE Design and Test of Computers , vol.22 , Issue.5 , pp. 414-421
    • Goossens, K.1    Dielissen, J.2    Rǎdulescu, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.