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Volumn , Issue , 2007, Pages 355-360

Implementation of AES/Rijndael on a dynamically reconfigurable architecture

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; DYNAMIC PROGRAMMING; PROGRAMMABLE LOGIC CONTROLLERS; THROUGHPUT;

EID: 34548356863     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364617     Document Type: Conference Paper
Times cited : (15)

References (24)
  • 3
    • 0003855464 scopus 로고    scopus 로고
    • 2nd ed. John Wiley and Sons. New York, NY
    • B. Schneier, Applied Cryptography, 2nd ed. John Wiley and Sons. New York, NY, 1996.
    • (1996) Applied Cryptography
    • Schneier, B.1
  • 4
    • 0036055207 scopus 로고    scopus 로고
    • System Design Methodologies for a Wireless Security Processing Platform
    • S. Ravi et al. System Design Methodologies for a Wireless Security Processing Platform, Proceedings on the DAC 2002.
    • (2002) Proceedings on the DAC
    • Ravi, S.1
  • 6
    • 34548360876 scopus 로고    scopus 로고
    • T. Wollinger et al. How well Are High-End DSPs Suited for the AES Algorithms? NIST AES-3 Conference, 2000.
    • T. Wollinger et al. How well Are High-End DSPs Suited for the AES Algorithms? NIST AES-3 Conference, 2000.
  • 8
    • 48149104394 scopus 로고    scopus 로고
    • Reconfigurable Memory Based AES Co-Processor
    • April
    • R. Chaves et al. Reconfigurable Memory Based AES Co-Processor, Proceedings of the RAW, April 2006
    • (2006) Proceedings of the RAW
    • Chaves, R.1
  • 13
    • 0036052456 scopus 로고    scopus 로고
    • Unlocking the Design Secrets of a 2.29 Gb/s Rijndael Processor
    • P.R. Schaumont, H. Kuo, I. Verbauwhede Unlocking the Design Secrets of a 2.29 Gb/s Rijndael Processor, DAC 2002.
    • DAC 2002
    • Schaumont, P.R.1    Kuo, H.2    Verbauwhede, I.3
  • 14
    • 34548350929 scopus 로고    scopus 로고
    • M2000 Embedded FPGA www.m2000.fr
    • M2000 Embedded FPGA www.m2000.fr
  • 15
    • 84947265882 scopus 로고    scopus 로고
    • Reconfigurable processor architectures for mobile phones
    • M. Vorbach, J. Becker, Reconfigurable processor architectures for mobile phones Proceedings on the IPDPS, 2003.
    • (2003) Proceedings on the IPDPS
    • Vorbach, M.1    Becker, J.2
  • 16
    • 0034187952 scopus 로고    scopus 로고
    • MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications
    • May
    • H. Singh et al. MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications, IEEE Transactions on Computers, May 2000.
    • (2000) IEEE Transactions on Computers
    • Singh, H.1
  • 20
    • 0242551725 scopus 로고    scopus 로고
    • A VLIWprocessor with reconfigurable instruction set for embedded applications
    • Nov
    • A. Lodi et al. A VLIWprocessor with reconfigurable instruction set for embedded applications, IEEE Journal of SolidState Circuit, Nov. 2003.
    • (2003) IEEE Journal of SolidState Circuit
    • Lodi, A.1
  • 21
    • 33746320641 scopus 로고    scopus 로고
    • A C-based Algorithm Development Flow for a Reconfigurable Processor Architecture
    • November
    • C. Mucci et al. A C-based Algorithm Development Flow for a Reconfigurable Processor Architecture, IEEE International Symposium on System on Chip, November 2003.
    • (2003) IEEE International Symposium on System on Chip
    • Mucci, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.