Hierarchical DFT methodology - A case study

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 847-856

  Remmers, Jeff ^a   Villalba, Moe ^a   Fisette, Richard ^b  

^a Plexus Design Solutions Inc   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY METHODOLOGY; HIERARCHICAL APPROACH; PHYSICAL DESIGN; SYSTEM ON CHIP DESIGN;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; HIERARCHICAL SYSTEMS; INPUT OUTPUT PROGRAMS; MICROPROCESSOR CHIPS; REAL TIME SYSTEMS;

DESIGN FOR TESTABILITY;

EID: 18144392000     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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