Leading-zero anticipatory logics for fast floating addition with carry propagation signal

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 1997, Pages 385-388

  Chang, Tsin Yuan ^a   Huang, Jing Reng ^a   Yang, Shao Sheng ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BOOLEAN ALGEBRA; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; MATHEMATICAL MODELS; TRANSISTORS; VLSI CIRCUITS;

CARRY PROPAGATION SIGNALS; FLOATING POINT (FLP) ADDERS; LEADING ZERO ANTICIPATORY (LZA) LOGICS;

LOGIC CIRCUITS;

EID: 0031344918     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)