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Volumn 2, Issue , 2003, Pages 1260-1264

Designing leading zeros anticipatory logic based on production rules

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC;

EID: 85008046319     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2003.1277444     Document Type: Conference Paper
Times cited : (1)

References (19)
  • 2
    • 0027908353 scopus 로고
    • Algorithmic design of a hierarchical and modulator leading zero detector circuit
    • V.G. Oklobdzija, "Algorithmic Design of a Hierarchical and Modulator Leading Zero Detector Circuit," Electronics Letters, vol. 29, no. 3, pp. 283-284, 1993.
    • (1993) Electronics Letters , vol.29 , Issue.3 , pp. 283-284
    • Oklobdzija, V.G.1
  • 4
    • 0028400635 scopus 로고
    • An algorithmic and novel design of a leading zero detector circuit: Comparison with logic synthesis
    • V.G. Oklobdzija, "An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis," IEEE Transactions on VLSI Systems, vol. 2, no. 1, pp. 124-128,1994.
    • (1994) IEEE Transactions on VLSI Systems , vol.2 , Issue.1 , pp. 124-128
    • Oklobdzija, V.G.1
  • 5
    • 85063333625 scopus 로고
    • UltrasparC: The next generation superscalar 64-bit SPARC
    • D. Greenley et al., "UltraSparc: The Next Generation Superscalar 64-bit Sparc," Proceedings of COMPCON'95, pp. 442-451, 1995
    • (1995) Proceedings of COMPCON'95 , pp. 442-451
    • Greenley, D.1
  • 11
    • 0025502603 scopus 로고
    • Second-generation RISC floating point with multiply-add fused
    • E. Hokenek, R. Montoye, and P. Cook, "Second-Generation RISC Floating Point with Multiply-Add Fused," IEEE Journal of Solid-State Circuits, vol. 25, no.5, pp. 1207-1213, 1990.
    • (1990) IEEE Journal of Solid-State Circuits , vol.25 , Issue.5 , pp. 1207-1213
    • Hokenek, E.1    Montoye, R.2    Cook, P.3
  • 13
    • 0025213823 scopus 로고
    • Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit
    • E. Hokenek, and R.K. Montoye, "Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit," IBM Journal of Research and Development, vol. 25, no. 5, pp. 71-77, 1990.
    • (1990) IBM Journal of Research and Development , vol.25 , Issue.5 , pp. 71-77
    • Hokenek, E.1    Montoye, R.K.2
  • 15
    • 0033682380 scopus 로고    scopus 로고
    • 1GHz leading zero anticipator using independent sign-bit determination logic
    • K.T. Lee, and K.J. Nowka, "1GHz Leading Zero Anticipator Using Independent Sign-Bit Determination Logic," Symposium on VLSI Circuits 2000, pp. 194-195, 2000.
    • (2000) Symposium on VLSI Circuits 2000 , pp. 194-195
    • Lee, K.T.1    Nowka, K.J.2
  • 16
    • 0033204413 scopus 로고    scopus 로고
    • Leading-one predication with concurrent position correction
    • J.D. Bruguera, and T.. Lang, "Leading-One Predication with Concurrent Position Correction," IEEE Transactions on Computers, vol. 48, no. 10, pp. 1083-1097, 1999.
    • (1999) IEEE Transactions on Computers , vol.48 , Issue.10 , pp. 1083-1097
    • Bruguera, J.D.1    Lang, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.