Leading-zero anticipatory logic for high-speed floating point addition

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 8, 1996, Pages 1157-1164

  Suzuki, Hiroaki ^b   Morinaka, Hiroyuki ^b   Makino, Hiroshi ^b   Nakase, Yasunobu ^b   Mashiko, Koichiro ^a,b   Sumi, Tadashi ^b  

^a IEEE

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN;

FLOATING POINT ADDITION (FADD); LEADING ZERO ANTICIPATORY (LZA) LOGIC;

LOGIC CIRCUITS;

EID: 0030213798     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508263     Document Type: Article

References (18)

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