A novel design of leading zero anticipation circuit with parallel error detection

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 676-679

  Zhang, Ge ^a,b   Qi, Zichu ^a,b   Hu, Weiwu ^a,b  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ADDITIONAL LOGIC; CIRCUIT IMPLEMENTATION; CRITICAL PATHS; DUAL PATH; FLOATING POINT UNITS; FLOATING-POINT ADDER; HIGH-SPEED; MICROPROCESSOR DESIGNS; NORMALIZATION PROCESS; NOVEL ALGORITHM; NOVEL DESIGN; PARALLEL EXECUTIONS; PATH DESIGN;

ADDERS; DESIGN;

ERROR DETECTION;

EID: 34547919687     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464678     Document Type: Conference Paper

References (9)

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