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Volumn 2006, Issue , 2006, Pages 1-14

FPGA-based reconfigurable measurement instruments with functionality defined by user

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSORS; REAL-TIME SWEEP; SOFTWARE-DEFINED INSTRUMENTATION (SDI); WAVEFORM GENERATORS;

EID: 33645143164     PISSN: 11108657     EISSN: None     Source Type: Journal    
DOI: 10.1155/ASP/2006/84340     Document Type: Article
Times cited : (10)

References (19)
  • 7
    • 27944439751 scopus 로고    scopus 로고
    • High speed signal sampler by multiple-path algorithm
    • Chiang Mai, Thailand, November
    • G.-R. Tsai and M.-C. Lin, "High speed signal sampler by multiple-path algorithm," in Proceeding of IEEE Region 10 Conference (TENCON'04), vol. 1, pp. 29-31, Chiang Mai, Thailand, November 2004.
    • (2004) Proceeding of IEEE Region 10 Conference (TENCON'04) , vol.1 , pp. 29-31
    • Tsai, G.-R.1    Lin, M.-C.2
  • 8
  • 10
    • 0032645526 scopus 로고    scopus 로고
    • Configurable logic for digital communications: Some signal processing perspectives
    • C. Dick and F. J. Harris, "Configurable logic for digital communications: some signal processing perspectives," IEEE Communications Magazine, vol. 37, no. 8, pp. 107-111, 1999.
    • (1999) IEEE Communications Magazine , vol.37 , Issue.8 , pp. 107-111
    • Dick, C.1    Harris, F.J.2
  • 12
    • 0019558620 scopus 로고
    • A survey of digital phase-locked loops
    • W. C. Lindsey and C. M. Chie, "A survey of digital phase-locked loops," Proceedings of the IEEE, vol. 69, no. 4, pp. 410-431, 1981.
    • (1981) Proceedings of the IEEE , vol.69 , Issue.4 , pp. 410-431
    • Lindsey, W.C.1    Chie, C.M.2
  • 14
    • 0037319509 scopus 로고    scopus 로고
    • An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time
    • T. Watanabe and S. Yamauchi, "An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time," IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 198-204, 2003.
    • (2003) IEEE Journal of Solid-state Circuits , vol.38 , Issue.2 , pp. 198-204
    • Watanabe, T.1    Yamauchi, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.