A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 12, 2004, Pages 1377-1381

  Wang, Chua Chin ^a   Tseng, Yih Long ^a   She, Hsien Chih ^b   Hu, Ron ^c  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b VastView Technology Inc   (Taiwan)

^c Asuka Semiconductor Inc   (Taiwan)

Author keywords

DLL; Frequency multiplier; Programmable

Indexed keywords

CASCADE CONNECTIONS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC CLOCKS; ELECTRIC LOSSES; FREQUENCY MULTIPLYING CIRCUITS; PHASE SHIFT; SPURIOUS SIGNAL NOISE; VOLTAGE CONTROL; WIRELESS TELECOMMUNICATION SYSTEMS;

DELAYED-LOCK LOOP (DLL); POWER DISSIPATION; PROGRAMMABLE FREQUENCY MULTIPLIERS; RADIO FREQUENCY (RF);

OSCILLATORS (ELECTRONIC);

EID: 12344335253     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.837997     Document Type: Article

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