A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Wei, Gu Yeon ^a   Stonick, John T ^b   Weinlader, Dan ^b   Sonntag, Jeff ^b   Searles, Shawn ^b  

^a HARVARD UNIVERSITY   (United States)

^b Accelerant Networks   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; JITTER; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; TRANSCEIVERS; TUNING; VARIABLE FREQUENCY OSCILLATORS;

CLOCK SYNTHESIZER; MULTIPLYING DELAY-LOCKED LOOP; MULTIPLYING PHASE-LOCKED LOOP; PHASE FREQUENCY DETECTOR; VOLTAGE CONTROLLED DELAY LINES;

CMOS INTEGRATED CIRCUITS;

EID: 0037630658     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. Sonntag, et al, "An Adaptive PAM-4 5Gb/s Backplane Transceiver in 0.25mm CMOS," CICC, 2002.
2. R. Farjad-Rad, et al, "A 0.2-2GHz 12mW Multiplying DLL for Low-Jitter Clock Synthesis in Highly-Integrated Data-Communication Chips," ISSCC Dig. Tech. Papers, pp. 76-77, 2002.
3. A. Waizman, "A Delay Line Loop for Frequency Synthesis of De-Skewed Clock," ISSCC Dig. Tech. Papers, pp. 298-299, 1994.
4. S.H. Wang, et al, "A 500-Mb/s Quadruple Data Rate SRAM Interface Using a Skew Cancellation Technique," J. Solid State Circuits, April 2001.