New schemes in clustered VLIW processors applied to turbo decoding

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2006, Pages 291-296

  Ituero, Pablo ^a   López Vallejo, Marisa ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; DATA ACQUISITION; ELECTRIC POWER UTILIZATION; OPTIMIZATION; PROGRAM PROCESSORS; TURBO CODES;

ASIP ARCHITECTURE; LEADING EDGE STANDARDS; SISO TURBO DECODING;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 34547487827     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2006.48     Document Type: Conference Paper

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