FPGA implementation of parallel Turbo-decoders

Proceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004

Volumn , Issue , 2004, Pages 198-203

  Thul, Michael J ^a   Wehn, Norbert ^a  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

FPGA Implementation; Parallel Architecture; Turbo Decoder; Wireless

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA TRANSFER; FIELD PROGRAMMABLE GATE ARRAYS; LOCAL AREA NETWORKS; MICROELECTRONICS; NATURAL FREQUENCIES; WIRELESS TELECOMMUNICATION SYSTEMS;

FORWARD ERROR CORRECTION (FEC) CODES; FPGA IMPLEMENTATION; MAXIMUM-A-POSTERIORI (MAP); PARALLEL ARCHITECTURE; RECURSIVE SYSTEMATIC CONVOLUTIONAL (RSC) ENCODERS;

TURBO CODES;

EID: 14244268071     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016568.1016622     Document Type: Conference Paper

References (16)

1. Third Generation Partnership Project, "3GPP home page," www.3gpp.org.
2. P. Paulin, J.-M. Balzano, A. Silburt, K. Van Berkel, R. Bramley, and N. Wehn, "Panel: "Chips of the Future: Soft, Crunchy or Hard?"," in Proc. 2004 Design Automation and Test in Europe (DATE '04), Paris, France, Feb. 2004.
3. M. J. Thul, F. Gilbert, T. Vogt, G. Kreiselmaier, and N. Wehn, "A Scalable System Architecture for High-Throughput Turbo-Decoders," in Proc. 2002 Workshop on Signal Processing Systems (SiPS '02), San Diego, California, USA, Oct. 2002, pp. 152-158.
4. J. Vogt, K. Koora, A. Finger, and G. Fettweis, "Comparison of Different Turbo Decoder Realizations for IMT-2000," in Proc. 1999 Global Telecommunications Conference (Globecom '99), Rio de Janeiro, Brazil, Dec. 1999, vol. 5, pp. 2704-2708.
5. F. Gilbert, F. Kienle, and N. Wehn, "Low Complexity Stopping Criteria for UMTS Turbo-Decoders," in Proc. 2003-Spring Vehicular Technology Confernce (VTC Spring '03), Jeju, Korea, Apr. 2003, pp. 2376-2380.
6. P. Robertson, P. Hoeher, and E. Villebrun, "Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding," European Transactions on Telecommunications (ETT), vol. 8, no. 2, pp. 119-125, March-April 1997.
7. A. Worm, P. Hoeher, and N. Wehn, "Turbo-Decoding without SNR Estimation," IEEE Communications Letters, vol. 4, no. 6, pp. 193-195, June 2000.
8. F. Kienle, H. Michel, F. Gilbert, and N. Wehn, "Efficient MAP-Algorithm Implementation on Programmable Architectures," in Kleinheubacher Berichte 2003, Miltenberg, Germany, Oct. 2002, vol. 46.
9. H. Dawid, G. Gehnen, and H. Meyr, "MAP Channel Decoding: Algorithm and VLSI Architecture," in VLSI Signal Processing VI, pp. 141-149. IEEE, 1993.
10. T.Miyauchi, K.Yamamoto, T. Yokokawa, M. Kan, Y. Mizutani, and M. Hattori, "High-Performance Programmable SISO Decoder VLSI Implementation for Decoding Turbo Codes," in Global Telecommunications Conference, 2001 (GLOBECOM '01), San Antonio, TX, USA, 2001, vol. 1, pp. 305-309.
11. B. Bougard, A. Giulietti, V. Derudder, J.-W. Weijers, S. Dupont, L. Hollevoet, F. Catthoor, L. van der Perre, H. De Man, and R. Lauwereins, "A Scalable 8.7nJ/bit 75.6Mb/s Parallel Concatenated Convolutional (Turbo-) CODEC," in Proc. 2003 IEEE International Solid-State Circuits Conference (ISSCC '03), San Francisco, CA, USA, feb 2003, pp. 152-153, 484.
12. R. Dobkin, M. Peleg, and R. Ginosar, "Parallel VLSI architecture for map turbo decoder," in 13th International Symposium on Personal, Indoor and Mobile Radio Communications 2002, 2002, vol. 1, pp. 384-388.
13. A. Nimbalker, K. T. Blankenship, B. Classon, T. E. Fuja, and D. J. Costello, "Inter-Window Shuffle Interleavers for High Throughput Turbo Decoding," in Proc. 3nd International Symposium on Turbo Codes & Related Topics, Brest, France, Sept. 2003, pp. 355-358.
14. T. Richter and G. Fettweis, "Parallel Interleaving on Parallel DSP Architectures," Proc. 2002 Workshop on Signal Processing Systems (SiPS '02), pp. 195-200, Oct. 2002.
15. M. J. Thul, F. Gilbert, and N. Wehn, "Optimized Concurrent Interleaving for High-Throughput Turbo-Decoding," in Proc. 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS '02), Dubrovnik, Croatia, Sept. 2002, pp. 1099-1102.
16. M. J. Thul, F. Gilbert, T. Vogt, G. Kreiselmaier, and N. Wehn, "A Scalable System Architecture for High-Throughput Turbo-Decoders," Journal of VLSI Signal Processing Systems (Special Issue on Signal Processing for Broadband Communications), vol. 39, no. 1/2, 2005, Kluwer Academic Publishers, Boston - to appear.