CMOS logic gates based on the minimum theoretical number of transistor in series

24th Norchip Conference, 2006

Volumn , Issue , 2006, Pages 85-88

  Schneider, Felipe R ^a   Reis, André I ^a   Ribas, Renato P ^b  

^a Nangate A/S   (Denmark)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; FUNCTION EVALUATION; LOGIC GATES; NETWORKS (CIRCUITS); TRANSISTORS;

CMOS LOGIC GATES; LOGIC PLANE; MULTIGATE CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 34547326110     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NORCHP.2006.329250     Document Type: Conference Paper

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