Design and synthesis of dynamic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 1, 2003, Pages 141-149

  Thorp, Tyler J ^a   Yee, Gin S ^b   Sechen, Carl M ^a  

^a University of Washington   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

Dynamic circuits; Logic synthesis; Monotonic circuits; Technology mapping

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC GATES; MICROPROCESSOR CHIPS;

DYNAMIC CIRCUITS;

VLSI CIRCUITS;

EID: 0345381745     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.800518     Document Type: Article

References (40)

1. D. Harris, "Skew-Tolerant Circuit Design," Ph.D., Stanford Univ., Stanford, CA, 1999.
2. R. Krambeck, C. Lee, and H. Law, "High-speed compact circuits with CMOS," IEEE J. Solid-State Circuits, vol. SC-17, pp. 614-619, June 1982.
3. B. Benschneider et al., "A 300-MHz 64-b quad-issue CMOS RISC microprocessor," IEEE J. Solid-State Circuits, vol. 30, pp. 1203-1214, Nov. 1995.
4. A. Charnas et al., "A 64 b microprocessor with multimedia support," in Proc. ISSCC Dig. Tech. Papers, Feb. 1995, pp. 177-179.
5. R. Colwell and R. Steck, "A 0.6 μm BiCMOS processor with dynamic execution," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 176-177.
6. H. Nambu et al., "A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM," in Proc. IEEE Int. Solid-State Circuits Conf., 1998, pp. 360-361.
7. J. Pretorius et al., "Latched domino CMOS logic," IEEE J. Solid-State Circuits, vol. SC-21, pp. 514-522, Aug. 1986.
8. G. Yee and C. Sechen, "Dynamic logic synthesis," in Proc. IEEE Custom Integrated Circuits Conf., May 1997, pp. 345-348.
9. V. Friedman and S. Liu, "Dynamic logic CMOS circuits," IEEE J. Solid-State Circuits, vol. SC-19, pp. 263-266, Apr. 1984.
10. L. Heller and W. Griffin, "Cascade voltage switch logic: A differential CMOS logic family," in Proc. ISSCC Dig. Tech. Papers, 1984, pp. 16-17.
11. C. Lee and E. Szeto, "Zipper CMOS," IEEE Circuits Devices Mag., pp. 10-16, May 1986.
12. F. Murabayashi et al., "2.5 V novel CMOS circuit techniques for a 150 MHz superscalar RISC processor," in Proc. 21st Eur. Solid-State Circuits Conf., 1995, pp. 178-181.
13. T. Thorp, G. Yee, and C. Sechen, "Monotonic static CMOS and dual Vt technology," in Proc. Int. Symp. Low Power Electronics and Design, 1999, pp. 151-155.
14. _, "Domino logic synthesis using complex static gates," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design. 1998, pp. 242-247.
15. D. Harris and M. Horowitz, "Skew-tolerant domino circuits," IEEE J. Solid-State Circuits, vol. 32, pp. 1702-1711, Nov. 1997.
16. Intel Corp., "Opportunistic Time-Borrowing Domino Logic," U.S. Patent #5 517 136, May 1996.
17. G. Yee et al., "Design tools and methodology for dynamic circuits," Trans. VLSI Design, to be published.
18. D. Kung and R. Puri, "Optimal P/N width ratio selection for standard cell libraries," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1999, pp. 178-185.
19. M. R. Prasad, D. Kirkpatrick, R. Brayton, and A. Sangiovanni-Vineentelli, "Domino logic synthesis and technology mapping," in Proc. Int. Workshop Logic Synthesis, May 1997.
20. R. Puri, A. Bjorksten, and T. Rosser, "Logic optimization by output phase assignment in dynamic logic synthesis," in IEEE/ACM Int. Conf. Computer-Aided Design, 1996, pp. 2-8.
21. V. G. Oklobdzija and R. K. Montoye, "Design-performance tradeoffs in CMOS domino logic," in Proc. IEEE'85 Custom Integrated Circuits Conf., May 1985, pp. 334-337.
22. J. Pretorius, A. Shubat, and C. Salama, "Charge redistribution and noise margins in domino CMOS logic," IEEE Trans. Circuits Syst., vol. CAS-33, pp. 786-793, Aug. 1986.
23. T. Williams, "Dynamic logic: Clocked and asynchronous," in Proc. ISSCC Dig. Tech. Papers, Tutorial 4, 1996.
24. A. Dharchoudhury et al., "Transistor-level sizing and timing verification of domino circuits in the power PC microprocessor," in Proc. IEEE Int. Conf. Computer Design, 1997, pp. 143-148.
25. G. De Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
26. R. Brayton, G. Hachtel, and A. Sangiovanni-Vincentelli, "Multilevel logic synthesis," Proc. IEEE, vol. 78, pp. 264-300, Feb. 1990.
27. M. Iyer, L. Stok, and A. Sullivan, "Wavefront technology mapping," in Proc. Int. Workshop Logic Synthesis, May 1998, pp. 419-426.
28. E. Lehman et al., "Logic decomposition during technology mapping," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1995, pp. 264-271.
29. E. Sentovich et al., "SIS: A System for Sequential Circuit Synthesis," Univ. California, Berkeley, CA, Tech. Rep. UCB/ERL M92/41, 1992.
30. Design Compiler Users Manual, Synopsys, Inc., Mountainview, CA, 1998.
31. E. Detjens et al., "Technology mapping in MIS," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1987, pp. 116-119.
32. K. Keutzer, "Dagon: Technology binding and local optimization by DAG matching," in Proc. Design Automation Conf., 1987, pp. 341-347.
33. J. Cong and Y. Ding, "Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1-12, Jan. 1994.
34. Y. Kukimoto, R. Brayton, and P. Sawkar, "Delay-optimal technology mapping by DAG covering," in Proc. Design Automation Conf., 1998, pp. 348-351.
35. M. Zhao and S. Sapatnekar, "Technology mapping for domino logic," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1998, pp. 276-281.
36. R. Brayton et al., "Automated implementation of switching functions as dynamic CMOS circuits," in Proc. IEEE Custom Integrated Circuits Conf., 1984, pp. 346-350.
37. _, "Method for optimizing logic for single-ended domino circuits," IBM Tech. Disclosure Bulletin, pp. 4398-4401, Dec. 1984.
38. G. De Micheli, "Performance-oriented synthesis of large-scale domino CMOS circuits," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 751-765, Sept. 1987.
39. M. Hofmann and A. Newton, "A domino CMOS logic synthesis system," in Proc. IEEE Int. Symp. Curcuits and Systems, 1985, pp. 411-414.
40. I. Sutherland et al., Logical Effort: Designing Fast CMOS Circuits. New York: Morgan Kaufmann, 1999.