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Volumn , Issue , 2006, Pages 3558-3561

Analysis of error control code use in ultra-low-power wireless sensor networks

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; ERROR CORRECTION; SIGNAL ENCODING;

EID: 34547326044     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (16)

References (21)
  • 2
    • 11244354258 scopus 로고    scopus 로고
    • Integrated Low-Power Communication System Design for Wireless Sensor Networks
    • December
    • T. H. Lin, W. Kaiser, and G. Pottie, "Integrated Low-Power Communication System Design for Wireless Sensor Networks", IEEE Communications Magazine, pp. 142-150, December 2004.
    • (2004) IEEE Communications Magazine , pp. 142-150
    • Lin, T.H.1    Kaiser, W.2    Pottie, G.3
  • 5
    • 12844285593 scopus 로고    scopus 로고
    • V. Ekanayake, C. Kelly IV, R. Manohar, An Ultra-low-power Processor for Sensor Networks, Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, October 2004.
    • V. Ekanayake, C. Kelly IV, R. Manohar, "An Ultra-low-power Processor for Sensor Networks", Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, October 2004.
  • 10
    • 0026187088 scopus 로고
    • Path Loss Prediction in Multifloored Buildings at 914 MHz
    • July
    • S.Y. Seidel and T.S. Rappaport, "Path Loss Prediction in Multifloored Buildings at 914 MHz", Electronics Letters, Vol. 27, no. 15, pp. 1384-1387, July 1991.
    • (1991) Electronics Letters , vol.27 , Issue.15 , pp. 1384-1387
    • Seidel, S.Y.1    Rappaport, T.S.2
  • 12
    • 21244468054 scopus 로고    scopus 로고
    • An assessment of VLSI and embedded software implementations, for Reed-Solomon decoders
    • Oct
    • T. S. Fill, P. G. Gulak, "An assessment of VLSI and embedded software implementations, for Reed-Solomon decoders", IEEE Workshop on Signal Processing Systems, SIPS '02, pp. 99-102, Oct. 2002.
    • (2002) IEEE Workshop on Signal Processing Systems, SIPS '02 , pp. 99-102
    • Fill, T.S.1    Gulak, P.G.2
  • 14
    • 4544275681 scopus 로고    scopus 로고
    • th European Solid-State Circuits Conference, ESSCIRC '03, pp. 723-726, Sept. 2003.
    • th European Solid-State Circuits Conference, ESSCIRC '03, pp. 723-726, Sept. 2003.
  • 16
    • 33750841340 scopus 로고    scopus 로고
    • Analog Iterative Error Control Decoders
    • thesis of Doctor of Philosophy, Dept. of Electrical & Computer Engineering, University of Alberta
    • C. Winstead, "Analog Iterative Error Control Decoders", thesis of Doctor of Philosophy, Dept. of Electrical & Computer Engineering, University of Alberta 2004.
    • (2004)
    • Winstead, C.1
  • 19
    • 0036504121 scopus 로고    scopus 로고
    • A 690-mW 1-Gb/s 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder
    • March
    • A.J. Blanksby, C.J., Howland, "A 690-mW 1-Gb/s 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder", IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404-412, March 2002.
    • (2002) IEEE Journal of Solid-State Circuits , vol.37 , Issue.3 , pp. 404-412
    • Blanksby, A.J.1    Howland, C.J.2
  • 21
    • 0016037512 scopus 로고
    • Optimal decoding of linear codes for minimizing symbol error rate
    • March
    • L.R. Bahl, J. Cocke, F. Jelinek, J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate", IEEE Trans. Information Theory, vol. 20, pp. 284-287, March 1974.
    • (1974) IEEE Trans. Information Theory , vol.20 , pp. 284-287
    • Bahl, L.R.1    Cocke, J.2    Jelinek, F.3    Raviv, J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.