Low-power asynchronous Viterbi decoder for wireless applications

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 286-289

  Kawokgy, Mohamed ^a   Salama, C André T ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Asynchronous; Bundled Data; Digital signal Processing; Four Phase; Handshaking Protocol; Low Power; Register transfer Level; Speed Independent; Synchronous; VHDL; Viterbi Algorithm; Wireless

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DATA TRANSFER; DIGITAL SIGNAL PROCESSING; NETWORK PROTOCOLS; SIGNAL ENCODING; WIRELESS TELECOMMUNICATION SYSTEMS;

ASYNCHRONOUS DECODERS; BUNDLED DATA; FOUR-PHASE; HANDSHAKING PROTOCOL; LOW POWER; REGISTER TRASFER LEVEL; SPEED INDEPENDENT; SYNCHRONOUS DECODERS; VHDL; VITERBI ALGORITHM;

DECODING;

EID: 16244400803     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013306     Document Type: Conference Paper

References (6)

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4. J. Sparso, and S. Furber (EDs.), "Principles of Asynchronous Circuit Design," Kluwer Academic Publishers, Boston, 2001.
5. Y. You, J. Wang, F. Lai, and Y. Ye, "VLSI Design and Implementation of High-Speed Viterbi Decoder," IEEE International Conference on Communications, vol. 1, pp. 64-68, 2002.
6. P. A. Riocreux, L. E. M. Brackenbury, M. Cumpstey, and S. B. Furber, "A Low-Power Self-Timed Viterbi Decoder," International Symposium on Advanced Research in Asynchronous Circuits and Systems, Proceedings, pp. 15 - 24, 2001.