A Double-Data Rate (DDR) Processing-in-Memory (PIM) device with WideWord floating-point capability

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 1933-1936

  Barrett, Tim ^a   Mediratta, Sumit ^a   Kwon, Taek Jun ^a   Singh, Ravinder ^a   Chandra, Sachit ^a   Sondeen, Jeff ^a   Draper, Jeffrey ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMODITY SYSTEMS; DATA-INTENSIVE ARCHITECTURE (DIVA) SYSTEM; DOUBLE-DATA RATE (DDR); PROCESSING-IN-MEMORY (PIM) DEVICES; SYSTEM INTEGRATION;

BANDWIDTH; DYNAMIC RANDOM ACCESS STORAGE; INTELLIGENT MATERIALS; INTERFACES (MATERIALS); PRODUCT DESIGN; PROJECT MANAGEMENT;

MICROPROCESSOR CHIPS;

EID: 34547281219     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. J. Adibi, H. Chalupsky, A. Valente, and E. Melz. The kojak group finder: Connecting the dots via integrated knowledge-based and statistical reasoning. In Innovative Applications of Artificial Intelligence IAAI 2004. American Association for Artificial Intelligence, 2004
2. Herming Chiueh, Jeffrey Draper, Sumit Mediratta, Jeff Sondeen, "The Address Translation Unit of the Data-Intensive Architecture (DIVA) System", Proceedings of the 28th European Solid-State Circuit Conference, September 2002
3. Jeff Draper, et al, "The Architecture of the DIVA Processing-In-Memory Chip", in Proc. of the International Conference on Supercomputing, June 2002
4. Jeffrey Draper, Jeff Sondeen, Chang Woo Kang, "Implementation of a 256-bit WideWord Processor for the Data-Intensive Architecture (DIVA) Processing-In-Memory (PIM) Chip", in Proc. of the 28th European Solid-State Circuit Conference, Sep. 2002
5. M. Hall and C. Steele. "Memory Management in a PIM-Based Architecture," in Proc. of the Workshop on Intelligent Memory Systems, October 2000
6. J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufman, Second Edition, 1996
7. HPC Challenge Benchmarks, http://icl.cs.utk.edu/hpcc/index.html
8. Intel Developer Documentation, http://www.developer.intel.com
9. JEDEC, http://www.jedec.org
10. Taek-Jun Kwon, Joong-Seok Moon, Jeff Sondeen, Jeff Draper. "An 0.18μm Implementation of a Floating-Point Unit for a Processing-In-Memory System", in Proc. of the International Symposium on Circuits and Systems, May 2004
11. Joong-Seok Moon, Taek-Jun Kwon, Jeff Sondeen, Jeff Draper, "An Area-Efficient Standard-Cell Floating-Point Unit Design for a Processing-In-Memory System", in Proc. of the 29th European Solid-State Circuit Conference, Sep. 2003
12. SUIF Compiler System, http://suif.stanford.edu