Implementation of a 256-bit wideword processor for the data-intensive architecture (DIVA) processing-in-memory (PIM) chip

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 77-80

  Draper, Jeffrey ^a   Sondeen, Jeff ^a   Kang, Chang Woo ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH LIMITEDS; BUILDING A PROTOTYPES; DATA PARALLELISM; DATA-INTENSIVE ARCHITECTURE SYSTEMS; DESIGN AND IMPLEMENTATIONS; M-TECHNOLOGIES; MEMORY BANDWIDTHS; PROCESSING-IN-MEMORY CHIPS;

DYNAMIC RANDOM ACCESS STORAGE; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS;

COMPUTER ARCHITECTURE;

EID: 13244254201     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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