SCOPUS 정보 검색 플랫폼

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 57-60

An area-efficient standard-cell floating-point unit design for a processing-in-memory system

(4) Moon, Joong Seok a Kwon, Taek Jun a Sondeen, Jeff a Draper, Jeff a

a UNIVERSITY OF SOUTHERN CALIFORNIA (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA-INTENSIVE ARCHITECTURE SYSTEMS; DESIGN AND IMPLEMENTATIONS; DIVISION ALGORITHMS; FLOATING POINT OPERATIONS; FLOATING POINT UNITS; FLOATING-POINT COMPUTATION; PROCESSING-IN-MEMORY CHIPS; PROCESSING-IN-MEMORY SYSTEMS;

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; MICROPROCESSOR CHIPS;

COMPUTER ARCHITECTURE;

EID: 13244270299 PISSN: 19308833 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ESSCIRC.2003.1257071 Document Type: Conference Paper

Times cited : (10)

References (9)

1
- 0037660160
- Memory management in pim-based systems
- Boston, MA
- M. Hall and C. Steele, "Memory Management in PIM-based Systems'', in Proc. of the workshop on intelligent memory systems, Boston, MA, 2000
- (2000) Proc. of the Workshop on Intelligent Memory Systems
- Hall, M.¹ Steele, C.²

2
- 0036374270
- The architecture of the diva processing-in- memory chip
- June
- Jeff Draper, et al, "The Architecture of the DIVA Processing-In- Memory Chip", Proc. of the International Conference on Supercomputing, June 2002
- (2002) Proc. of the International Conference on Supercomputing
- Draper, J.¹

3
- 13244254201
- Implementation of a 256-bit wideword processor for the data-intensive architecture (diva) processing-in-memory (pim) chip
- Sep
- Jeffrey Draper, Jeff Sondeen, Chang Woo Kang, "Implementation of a 256-bit WideWord Processor for the Data-Intensive Architecture (DIVA) Processing-In-Memory (PIM) Chip", Proc. of the 28th European Solid-state Circuit Conference, Sep. 2002
- (2002) Proc. of the 28th European Solid-state Circuit Conference
- Draper, J.¹ Sondeen, J.² Kang, C.W.³

4
- 12444317990
- Implementation of a 32-bit risc processor for the data-intensive architecture processing-in-memory chip
- Architectures, and Processors, July
- Jeffrey Draper, et al, "Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip", Proc. of the IEEE International Conference on Application- Specific Systems, Architectures, and Processors, July 2002
- (2002) Proc. of the IEEE International Conference on Application- Specific Systems
- Draper, J.¹

5
- 0003589321
- IEEE standard for binary floating-point arithmetic
- "IEEE Standard for Binary Floating-point Arithmetic", ANSI/IEEE Standard 754, 1985
- (1985) ANSI/IEEE Standard , vol.754

6
- 0006480330
- Ph. D. dissertation, Stanford University, Feb.
- A. Liddicoat, "High-Performance Arithmetic for Division and the Elementary Function", Ph. D. dissertation, Stanford University, Feb. 2002
- (2002) High-Performance Arithmetic for Division and the Elementary Function
- Liddicoat, A.¹

7
- 84969570347
- High-performance floating-point divide
- Sep
- A. Liddicoat and M. J. Flynn, "High-Performance Floating-point Divide", Euromicro Symposium on Digital System Design, Sep. 2001
- (2001) Euromicro Symposium on Digital System Design
- Liddicoat, A.¹ Flynn, M.J.²

8
- 0008607167
- Synopsys Inc
- Module Compiler User Guide, Synopsys Inc.
- Module Compiler User Guide

9
- 11844261775
- Synopsys Inc
- Nanosim User Guide, Synopsys Inc.
- Nanosim User Guide

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.