The address translation unit of the data-intensive architecture (DIVA) system

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 767-770

  Chiueh, Herming ^a   Draper, Jeffrey ^b   Mediratta, Sumit ^b   Sondeen, Jeff ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS TRANSLATION; APPLICATION CODES; CO-PROCESSORS; DATA-INTENSIVE ARCHITECTURE SYSTEMS; MEMORY BANDWIDTHS; MULTIMEDIA APPLICATIONS; PROCESSING-IN-MEMORY CHIPS; VLSI DESIGN;

MATRIX ALGEBRA;

MICROPROCESSOR CHIPS;

EID: 84893720979     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. Mitsubishi, ":M32R/D Series: 32-bit RISC Processor, Onchip DRAM," www.mitsubishichips. com/data/datasheets/mcus/m32rdgrp.html, May 6, 1999.
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6. M. Hall, P. Kogge, J. Koller, P. Diniz, J. Chame, J. Draper, J. LaCoss, J. Granacki, J. Brockman, W. Athas, A. Srivastava, J. Shin, and J. Park, "Mapping Irregular Computations to DIVA, a Data-Intensive Architecture," in Proc. of SC '99, 1999.
7. J. Draper, I. Kim, J. Sondeen, and S. Mediratta, "Implementation of a 32-bit RISC Scalar Processor for the Data-Intensive Architecture (DIVA) Processing-In-Memory (PIM) Chip," Submitted to International Conference on Application-Specific Systems, Architectures, and Processors (ASAP), 2002.
8. J. Draper, C. W. Kang, and J. Sondeen, "Implementation of a 256-bit Wide Word Processor for the Data-Intensive Architecture (DIVA) Processing-In-Memory (PIM) Chip," Submitted to ESSCIRC, 2002.