A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 168-169

  Hwang, I ^a   Lee, S ^a,a   Kim, S ^a  

^a Korea University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CLOSED LOOP CONTROL SYSTEMS; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; FREQUENCY RESPONSE; FREQUENCY STABILITY; GAIN CONTROL; PHASE MEASUREMENT; TIMING CIRCUITS; TIMING JITTER; TUNING;

CLOCK SYNTHESIS APPLICATIONS; DIGITALLY CONTROLLED PHASE-LOCKED LOOPS (DCPLL);

PHASE LOCKED LOOPS;

EID: 0034428308     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A monolithic CMOS 10MHz DPLL for burst-mode data retiming
2. An all-digital phase-locked loop with 50-cycle lock time suitable for high performance microprocessors
3. A 250MHz low jitter adaptive bandwidth PLL